Conference Paper

FPGA Implementation of Encoder for (15, k) Binary BCH Code Using VHDL and Performance Comparison for Multiple Error Correction Control

DOI: 10.1109/CSNT.2012.170 Conference: IEEE International Conference on Communication Systems and Network Technologies, Volume: 2
In this paper we have designed and implemented (15, k) a BCH Encoder on FPGA using VHDL for reliable data transfer in AWGN channel with multiple error correction control. The digital logic implementation of binary encoding of multiple error correcting BCH code (15, k) of length n=15 over GF (2 4) with irreducible primitive polynomial x 4 +x+1 is organised into shift register circuits. Using the cyclic codes, the reminder b(x) can be obtained in a linear (15-k) stage shift register with feedback connections corresponding to the coefficients of the generated polynomial. Three encoder are designed using VHDL to encode the single, double and triple error correcting BCH code (15, k) corresponding to the coefficient of generated polynomial. Information bit is transmitted in unchanged form upto k clock cycles and during this period parity bits are calculated in the LFSR then the parity bits are transmitted from k+1 to 15 clock cycles. Total 15-k numbers of parity bits with k information bits are transmitted in 15 codeword. Here we have implemented (15, 5, 3), (15, 7, 2) and (15, 11, 1) BCH code encoder on Xilinx Spartan 3 FPGA using VHDL and the simulation & synthesis are done using Xilinx ISE 10.1. Also a comparative performance based on synthesis & simulation on FPGA is presented.
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    • "They can correct one bit error in any position of 7 bit data. The synthesis and simulations were carried out using Xilinx and implemented on Spartan 3 FPGA a (15, k) BCH encoder [7]. The result presented from the synthesis and timing simulation, shows the (15, 5, 3) BCH Encoder is more advantageous over the other two, according to speed requirement. "
    [Show abstract] [Hide abstract] ABSTRACT: Error Correcting Codes are required to have a reliable communication through a medium that has an unacceptable bit error rate and low signal to noise ratio. In IEEE 802.15.6 2.4GHz Wireless Body Area Network (WBAN), data gets corrupted during the transmission and reception due to noises and interferences. Ultra low power operation is crucial to prolong the life of implantable devices. Hence simple block codes like BCH (63, 51, 2) can be employed in the transceiver design of 802.15.6 Narrowband PHY. In this paper, implementation of BCH (63, 51, t = 2) Encoder and Decoder using VHDL is discussed. The incoming 51 bits are encoded into 63 bit code word using (63, 51) BCH encoder. It can detect and correct up to 2 random errors. The design of an encoder is implemented using Linear Feed Back Shift Register (LFSR) for polynomial division and the decoder design is based on syndrome calculator, inversion-less Berlekamp-Massey algorithm (BMA) and Chien search algorithm. Synthesis and simulation were carried out using Xilinx ISE 14.2 and ModelSim 10.1c. The codes are implemented over Virtex 4 FPGA device and tested on DN8000K10PCIE Logic Emulation Board. To the best of our knowledge, it is the first time an implementation of (63, 51) BCH encoder and decoder carried out.
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  • [Show abstract] [Hide abstract] ABSTRACT: Abstract— This paper presents the FPGA implementation of Narrowband Physical Layer architecture for Wireless Body Area Network (WBAN) based on IEEE 802.15.6–2012 standard. An abstract level hardware implementation of the most matured Narrowband (NB) PHY operating at 2.4 GHz ISM band among the three PHY layers defined by the standard is proposed. Major building blocks of PHY transceiver such as CRC, spreader, interleaver and scrambler were individually designed and integrated. To avoid the inherent limitation of the data transmission and to achieve higher reliability especially for medical applications, BCH (63, 51, 2) encoder and decoder is integrated to the design. Before modulation, spreading technique is employed and supports pi/2 DBPSK modulation. The transceiver achieves a data rate of 121.4 kbps and packet size of 256 bits. The design has been simulated in Questa 10.1.d, synthesized in Xilinx ISE 14.4 and successfully implemented and tested on ML605 Evaluation Board through PCIe interface. The proposed design can interact with Microblaze processor and the board can be interfaced with Analog Communication Board, AD-FCOMMS1-EBZ.
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  • [Show abstract] [Hide abstract] ABSTRACT: A FPGA based digital system design is one of the real time applications in the dynamic environment. The reliability of the devices measured through the various fault diagnosis. FPGA based devices either independent or a dependent to the application. In this paper, the fault diagnosis based on Low Density Parity Check (LDPC) is proposed. The C432 benchmark circuit is programmed with LDPC scheme to diagnosis the stuck at faultsin the circuit. The iterative shifting of bits in the register check the fault in the circuit.The benchmark circuit performance reveals the efficient fault diagnosis based on LDPC scheme. The comparative analysis between the Bose, Chaudhuri, and Hocquenghem (BCH) and proposed LDPC confirms the effective fault diagnosis in FPGA.
    No preview · Article · Jan 2015 · International Journal of Applied Engineering Research
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