Imaging photomultiplier array with integrated amplifiers and high-speed USB interface

Abstract

Multianode photomultiplier tube (PMT) arrays are finding application as convenient high-speed light sensitive devices for plasma imaging. This paper describes the development of a USB-based "plug-n-play" 16-channel PMT camera with 16 bits simultaneous acquisition of 16 signal channels at rates up to 2 MSs per channel. The preamplifiers and digital hardware are packaged in a compact housing which incorporates magnetic shielding, on-board generation of the high-voltage PMT bias, an optical filter mount and slits, and F-mount lens adaptor. Triggering, timing, and acquisition are handled by four field-programmable gate arrays (FPGAs) under instruction from a master FPGA controlled by a computer with a LABVIEW interface. We present technical design details and specifications and illustrate performance with high-speed images obtained on the H-1 heliac at the ANU.

Full text

Imaging photomultiplier array with integrated amplifiers and high-speed
USB interfacea…
M. Blacksell, J. Wach, D. Anderson, J. Howard, S. M. Collis, B. D. Blackwell,
D. Andruczyk,b兲and B. W. Jamesc兲
Plasma Research Laboratory, Australian National University, Canberra, Australian Capital
Territory 0200, Australia
共Presented 15 May 2008; received 12 May 2008; accepted 7 July 2008;
published online 31 October 2008兲
Multianode photomultiplier tube 共PMT兲arrays are finding application as convenient high-speed
light sensitive devices for plasma imaging. This paper describes the development of a USB-based
“plug-n-play” 16-channel PMT camera with 16 bits simultaneous acquisition of 16 signal channels
at rates up to 2 MS/s per channel. The preamplifiers and digital hardware are packaged in a compact
housing which incorporates magnetic shielding, on-board generation of the high-voltage PMT bias,
an optical filter mount and slits, and F-mount lens adaptor. Triggering, timing, and acquisition are
handled by four field-programmable gate arrays 共FPGAs兲under instruction from a master FPGA
controlled by a computer with a LABVIEW interface. We present technical design details and
specifications and illustrate performance with high-speed images obtained on the H-1 heliac at the
ANU. © 2008 American Institute of Physics. 关DOI: 10.1063/1.2965013兴
I. INTRODUCTION
With high-gain, low noise, and subnanosecond response
times, photomultiplier arrays1offer many advantages for
high-speed plasma optical imaging2,3and in conjunction with
an appropriate scintillator, for imaging soft x-ray plasma
emission.4Multiple 16-channel arrays have been used for
time-resolved Doppler spectroscopy on the H-1 heliac at the
Australian National University5,6and using an 8⫻8 multian-
ode detector array for tomographic imaging of plasma
fluctuations.7The devices are also used in a wide number of
other applications in nuclear science and medicine.
To be successfully deployed, the parallel photomultiplier
tube 共PMT兲signals need to be appropriately amplified and
digitally acquired. Initially, for the H-1 systems, stand-alone
arrays of 500 kHz bandwidth transimpedance amplifiers
were constructed to amplify and buffer the signals prior to
high-speed CAMAC-based digitization. To minimize noise,
the detector and amplifier arrays were subsequently encapsu-
lated in a cylindrical PMT housing, which also accommo-
dated
␮
-metal shielding, a slit and filter assembly, and
F-mount lens adaptor. A photograph of this earlier arrange-
ment is shown in Fig. 1. These compact integrated systems
were successfully deployed for electron temperature profile
measurements on H-1 obtained by imaging and subsequently
calculating the intensity ratio of selected atomic helium
emission lines from a repetitively pulsed, injected supersonic
neutral helium beam.8Typical data are shown in Fig. 2.
Given the utility of these devices for general purpose
high-speed imaging, we have undertaken to develop a fully
integrated, high-speed USB-based “plug-n-play” unit. The
16-channel unit is designed to incorporate necessary optical
components, magnetic shielding, an internal high voltage
supply for the PMT tube, transimpedance amplifiers, 16 bits,
2MS/s data acquisition, on-board memory, and high-speed
USB communications interface. The back panel has just four
connectors: the USB socket, power connector and external
trigger, and acquisition clock inputs. This article describes
the electronic layout and mechanical construction of the
compact 16-channel camera that is being developed for high-
speed optical spectroscopy on the H-1 heliac at the ANU.
II. HARDWARE OVERVIEW
The mechanical layout for the PMT camera is shown in
Fig. 3. The system accommodates a linear 16-channel
Hamamatsu PMT array. The electronics, optics, detector, and
shielding are compactly mounted within a 75 mm diameter
aluminum tube with length of 210 mm which is usually sup-
ported on a standard optical mounting rail. A spigot on the
front plate accommodates a Nikon F-mount lens adaptor for
imaging the external scene. The PMT array and socket are
mounted on an internal rail that allows the distance between
a兲Contributed paper, published as part of the Proceedings of the 17th Topical
Conference on High-Temperature Plasma Diagnostics, Albuquerque, New
Mexico, May 2008.
b兲Also at Max-Planck-Institut für Plasmaphysik, Greifswald 17491,
Germany.
c兲Also at School of Physics, University of Sydney, New South Wales 2006,
Australia.
FIG. 1. 共Color online兲Photograph of the first version of the integrated PMT
and amplifier array.
REVIEW OF SCIENTIFIC INSTRUMENTS 79, 10F506 共2008兲
0034-6748/2008/79共10兲/10F506/3/$23.00 © 2008 American Institute of Physics79, 10F506-1
Downloaded 29 Jun 2010 to 130.56.65.35. Redistribution subject to AIP license or copyright; see http://rsi.aip.org/rsi/copyright.jsp

the camera lens and detector to be adjusted for optimum
focusing. The detector is enclosed by a close fitting
␮
-metal
jacket which helps minimize sensitivity to external magnetic
fields. Because the sensitive area for each of the 16 detecting
surfaces is ⬃30⫻1mm
2, provision has been made for the
insertion of slit apertures in close proximity to the detector
array front surface in order to limit the field of view. In front
of the slit is an enclosure to accommodate standard 1 in.
color filters.
III. ELECTRONICS
The electronics consists of sixteen transimpedance am-
plifiers, 16 analog to digital converters 共ADCs兲, four field
programmable gate array 共FPGA兲devices to control the four
ADC boards 共four ADCs per board兲, a master FPGA to pro-
cess commands and transfer data, and a USB transceiver.
The front-end amplifier module and back-end digital hard-
ware unit are connected via an interface card that acts as a
break point allowing easy interchange of analog preamplifier
units in case it is required to change gain or bandwidth. A
block diagram of the circuitry is given in Fig. 4.
A. Transimpedance amplifiers
The transimpedance amplifiers convert and filter the cur-
rent from the PMT array to a voltage that is sampled by the
ADCs. The transimpedance amplifiers use a low noise
共5.4 nV/冑Hz兲, high impedance 共1G⍀兲, wide gain band-
width 共180 MHz兲field effect transistor 共FET兲operational
amplifier 共THS4601兲to maintain a virtual ground and to
minimize loss of signal current. The THS4061 output drives
a wide gain bandwidth 共300 MHz兲current feedback opera-
tional amplifier 共THS3061兲to provide the feedback current
drive to maintain a flat gain 共ⱗ1dB兲兲and to minimize
group delay 共艋50 ns兲through the filter passband
共艋500 kHz兲. The maximum input current specified for this
unit is 10
␮
A. The gain and bandwidth of the unit can be
changed by replacing a resistor and capacitor respectively.
B. Analog to digital converters
Four ADCs are mounted on a circular board and are
controlled by one FPGA. Four such boards and FPGAs are
FIG. 3. 共Color online兲Front view mechanical drawing of the PMT assembly showing ADC and master FPGA boards.
FIG. 2. 共Color online兲16-channel light emission data at 504 nm during
multipulse supersonic helium beam injection into an electron-cyclotron
heated H–He discharge at 0.5 T in the H-1 heliac.
10F506-2 Blacksell et al. Rev. Sci. Instrum. 79, 10F506 共2008兲
Downloaded 29 Jun 2010 to 130.56.65.35. Redistribution subject to AIP license or copyright; see http://rsi.aip.org/rsi/copyright.jsp

required for acquisition of all 16 channels. The ADCs used
are 16 bits, 2 MS/s, successive approximation register with
parallel interface 共ADS8411兲. An ultralow noise reference
共1.8
␮
V voltage noise 0.1– 10 Hz, ADR444兲is used to pro-
vide the 4.096 V reference for the unipolar input of the ADC
and is common between all 16 ADCs. Low noise power sup-
plies 共⬍125
␮
V兲provide the 5 V used for the analog section
of the ADC’s. The power supply uses a ADR444 reference
providing an ultralow noise reference for a low noise
共6nV/冑Hz兲, precision 共⬍100
␮
V offset兲operational ampli-
fier 共AD8620兲that drives the gate of a series pass regulator
FET. A similar power supply provides the transimpedance
amplifiers with a low noise bipolar 共⫾6.6 V兲power supply.
C. Analog to digital converter FPGA controller
The FPGA 共Altera Cyclone 2 EP2C20F256C6兲simulta-
neously reads the four 16 bit outputs from the ADCs and
writes them to the DDR2 memory 共Micron
MT47H64M16HR兲. The memory has 1 Gbit capacity and
can store up to ⬃7.8 s of data at the maximum sampling rate
of the ADC’s. The memory operates at a clock rate of
166 MHz and is a 4nbit architecture ideal for completing
memory transfers so as to not impede the maximum sam-
pling rate of the ADCs. To further minimize noise in the
ADC during the crucial conversion stage the DDR2 memory
clock circuitry can be disabled thereby removing exposure of
the ADC to fast switching digital edges.
D. Master FPGA controller/USB/HV module
The master FPGA 共EP2C20F256C6兲is responsible for
managing data transfer from the four ADC FPGAs and for
handling commands from the USB 2.0 transceiver
共CY7C68001兲. The various clock, trigger, and data acquisi-
tion configurations are established over the USB interface
under software control.
The sample clock can be either generated internally or
user supplied for synchronization with an external clock
source. If generated internally the master FPGA will clock
the ADC’s at the rate set by software. Both “start” and “stop”
trigger modes are supported. In start trigger mode a preset
number of samples is acquired following either an externally
supplied or internally USB generated trigger. In stop trigger
mode, the unit will continuously acquire samples until an
external stop trigger is received, whereupon a predefined
number of pre- and post-trigger samples are stored.
The master FPGA sets the stable PMT high voltage sup-
plied by a 1 kV source 共EMCO C10, Ripple p-p ¡50 mV兲by
programming an 8 bit digital to analog converter 共DAC兲
共AD5601兲. The control voltage from the DAC sets an output
resolution of ⬃4 V for the 1 kV source. Reset circuitry
共LTC1326-2.5兲on the USB board monitors power supplies
for failure conditions during operation and protects the FP-
GAs during power up. After power supplies have stabilized
at their operating voltage, all FPGA’s are released from their
reset condition to allow programming and operation.
For improved data integrity and to minimize board space
and costs, we have employed DDR2 memory, which features
internal data-line termination resistors共on-die termination兲,
to store the data transferred from the FPGA. A reference
regulator 共TPS51100兲on the FPGA boards supplies voltages
for the DDR2 termination pull-up resistors and also supplies
a stable reference voltage for the memory devices.
The master FPGA board contains the serial configuration
device 共EPCS16兲which is controlled by the master FPGA.
After the master FPGA has been programed the four ADC
FPGAs are programed too. This serial configuration scheme
allows for one serial configuration device and one in-circuit
programming connector to program new code for all FPGAs.
The software to control the unit has been written in LABVIEW
and can be compiled into dynamic linked libraries for use
with other languages. The LABVIEW program can be ex-
tended to allow post-data-processing.
E. Future developments
Further plans to modify the unit include a high-speed
interface from ADC FPGAs to the master FPGA to allow
streaming of data to the PC during acquisition. This will
allow data record length to be extended beyond that permit-
ted by the on-board memory device. The unit will also be
modified to include a transmission control protocol/internet
protocol board which can replace the USB board. With avail-
able FPGA resources real time data processing, demodula-
tion and compression of data can be performed.
1See http://sales.hamamatsu.com/multianode for information about multi-
channel photo-tube arrays.
2R. G. O’Neill, R. J. Smith, C. Akcay, W. T. Hamp, R. Z. Aboul Hosn, T.
R. Jarboe, A. J. Redd, P. E. Sieck, G. L. Sutphin, J. S. Wrobel, and HIT-SI
Team, J. Fusion Energy 66, 131 共2007兲.
3N. Asakura, M. Takechi, N. Oyama, and T. Nakano, J. Nucl. Mater. 337–
339, 712 共2005兲.
4L. Delgado-Aparicio, D. Stutman, K. Tritz, M. Finkenthal, R. Kaita, L.
Roquemore, D. Johnson, and R. Majeski, Rev. Sci. Instrum. 75, 4020
共2004兲.
5J. Howard, C. Michael, F. Glass, and A. Cheetham, Rev. Sci. Instrum. 72,
888 共2001兲.
6C. Michael, J. Howard, and B. D. Blackwell, Rev. Sci. Instrum. 72, 1034
共2001兲.
7F. Glass, J. Howard, and B. Blackwell, IEEE Trans. Plasma Sci. 33,472
共2005兲.
8D. Andruczyk, S. Namba, B. W. James, K. Takiyama, and T. Oda, Plasma
Devices Oper. 14,81共2006兲.
Digi tal
Analog
Analog
Digi tal
AnalogAnalog
Di
g
i
ta
l
Di
g
i
ta
l
Analog
USB
T
RIGGER
CLOCK
POWER
PMT
ARRAY
HIGH
VOLTAGE
MODULE
SIXTEEN
TRAN SIMPEDANC E
AMPLIF IERS
INTER-
CONNECT
BOARD
ADCs
MASTER
FPGA
USB
FIG. 4. 共Color online兲Block diagram of PMT-camera electronics. See text for discussion.
10F506-3 Imaging photomultiplier array Rev. Sci. Instrum. 79, 10F506 共2008兲
Downloaded 29 Jun 2010 to 130.56.65.35. Redistribution subject to AIP license or copyright; see http://rsi.aip.org/rsi/copyright.jsp