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Optimization of Image‐Processing Algorithms Using FPGAs
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Digital image processing and computer vision are rapidly evolving research fields with growing number of applications also for military purposes. Digital systems designed for military applications, such as tactical and strategic surveillance, self-guided armaments and remote or autonomously guided vehicles, often require both fast processing and flexibility. The latter is needed to rapidly support on-demand modifications during the circuit operations. This feature makes Field Programmable Gate Arrays (FPGAs) the most attractive solution to support these applications. This paper presents a new Single Instruction Multiple Data (SIMD) 2-D convolver purposely designed for FPGA-based image and video processors. The proposed architecture can dynamically adapt itself to different bit resolutions of image pixels and kernel weights avoiding power and time-consuming reconfiguration. This property is obtained thanks to new SIMD arithmetic circuits purposely designed for the proposed convolver and optimized for the FPGA platform. The circuit presented in this work can be efficiently exploited in all the applications requiring real-time adaptive convolutions. The new convolver has been characterized using VIRTEX XILINX devices but it can be efficiently implemented also in different FPGA device families.
As part of the solution to the automatic compilation problem, a
discussion of the analysis performed on a set of morphological vision
procedures developed by vision experts is presented. The basic
definitions for both binary and gray-scale morphological operators are
reviewed. Examples of morphological algorithms developed by vision
experts are described. Comments regarding the solution of automatic
compilation of vision procedures are given
For the purposes of object or defect identification required in industrial vision applications, the operations of mathematical morphology are more useful than the convolution operations employed in signal processing because the morphological operators relate directly to shape. The tutorial provided in this paper reviews both binary morphology and gray scale morphology, covering the operations of dilation, erosion, opening, and closing and their relations. Examples are given for each morphological concept and explanations are given for many of their interrelationships.
In this paper, we present the results obtained inside the research line SIRVA of the project TRACER. We can summarize these results in two aspects. On the one hand, a client/server Internet system has been developed. This system provides services of image processing via web by means of algorithms implemented in reconfigurable circuits (FPGAs). In this way, we offer a platform open to the scientific community, through a well-prepared communication system, providing the reconfigurable computing advantages where these resources are not physically available. Furthermore, this platform allows the performance comparison between the software and hardware (FPGA) implementation of the same image processing operation. Therefore, users, via the Internet and from anywhere, can check in a practical way the performance improvement produced by the FPGA use (in fact, some of our FPGA-based implementations are even more than 139 times faster than the corresponding software implementation), redounding to a greater diffusion of the FPGA virtues. On the other hand, a web repository of artificial-vision problems has also been created with growing dimensions, including a complete description of each problem, hardware and software solutions, practical results and links of interest. This repository is open to any external collaboration, being very easy to extend it with the description of new artificial-vision problems or adding new languages to existent descriptions.
Addition is a fundamental operation for the convolution (FIR filters). In FPGAs, addition should be carried out in a standard way employing ripple-carry adders (rather than carry-save adders), which complicates search for an optimal adder structure as routing order has a substantial influence on the addition cost. Further, complex parameters of inputs to the adders tree have been considered, e.g. correlation between inputs. These parameters are specified in different ways for different convolver architectures: Multiplierless Multiplication, Look-Up Table based Multiplication, Distributed Arithmetic. Furthermore, optimization techniques: Exhaustive Search and Greedy Algorithm have been implemented, and as a result, the Greedy Algorithm is the best solution when time of computation is of great importance. Otherwise, the Exhaustive Search should be employed for the number of the addition inputs n⩽8. This paper is a part of the research on the AuToCon-Automated Tool for generating Convolution in FPGAs
In FPGAs, an addition should be carried out in the standard way employing ripple-carry adders (rather than carry-save adders), which complicates search for an optimal adder structure as routing order has a substantial influence on the addition cost. Further, complex parameters of inputs to the adder block have been considered e.g. correlation between inputs. These parameters are specified in different ways for different convolver architectures. Consequently optimisation of the adder tree is a key issue addressed in this paper. Simulated Annealing and Genetic Programming have been proposed, and obtained results compared with the Greedy Algorithm (GrA) and the Exhaustive Search (ES). As a result, the GrA is the best solution when computation time is of great importance. Otherwise, the Simulated Annealing should be employed for the number of addition inputs N>8, and the ES is recommended for N⩽8. Employing the Simulated Annealing gives about 10-20% area reduction in comparison to the GrA