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Numerical analysis on the effects of different inlet gates and gap heights in TQFP encapsulation process
Abstract
Finite volume method (FVM) based simulation of encapsulation process in thin quad flat pack (TQFP) packages is presented in this paper. The 3D model of TQFP package is built and meshed with tetrahedral elements using GAMBIT, and simulated by FLUENT software. Castro-Macosko viscosity model and volume of fluid (VOF) technique are applied for flow front tracking of the encapsulant. Curing kinetics is taken into consideration in the simulation using Kamal's equation. To solve the Castro-Macosko and Kamal models, suitable user defined functions (UDFs) are developed using MS VISUAL STUDIO.NET software and incorporated into the FLUENT. The parameters such as mold filling time, flow front profiles, pressure distribution in the package and void formation, for three different inlet gate arrangements and gap heights, are analyzed. The degree of conversion of the molding compound during the encapsulation process is also studied for different number of inlet gates. It is found that the filling time and void occurrence could be reduced by increasing the number of inlet gates, and the variation of gap height within the cavity is crucial in controlling the peak pressure. Moreover, the combined effect to two competing events, such as, reduction of viscosity with shear rate due to non-Newtonian behavior of the polymer fluid and increase in viscosity during the curing reaction, are effectively demonstrated. The simulation results are compared with previous experimental results and found in good conformity. © 2011 Elsevier Ltd. All rights reserved.
... Moreover, the Castro−Makosco viscosity model was employed to describe the polymerization and to model the viscosity of moulding compound. The Castro-Macosko model, which provides more reliable predictions on flow rheology had been used by Jong et al. [2], and Khor et al. [8] in their integrated circuits (IC) simulation. By considering Castro-Macosko models, molten EMC behaves more or less as Newtonian fluid with the change in viscosity being the non-Newtonian aspect during the encapsulation process. ...
... TABLE I summarizes the material properties of the EMC [6 and 13]. The boundary and initial conditions are as follows [8]: In the simulation, the PBGA is modelled as a 3-D finite volume grid. The dimension of the mould model is 30 mm × 30 mm × 1.17 mm. ...
... Moreover, the mould temperature is set as 175 °C, and 0.3 m/s of inlet velocity is applied during the encapsulation process. The simulation was performed on an Intel Core 2 Duo processor E7500, 2.93 GHz with 2 GB of RAM; it took around 12 hours in each case to complete the 14000 iterations using 0.001 s of time step size [8]. The commercial FEM based software ABAQUS is used in this study to calculate the wire deformation. ...
This paper presents the optimization of the Plastic Ball Grid Array (PBGA) package during the encapsulation process. Optimized design of the PBGA package enhances the encapsulation process and minimizes the stress and deformation on the wires. The physical and process parameters (i.e., pressure inlet, diameter of wire, vent height, and mould filled time) were optimized via response surface methodology using central composite design (CCD) to minimize the stress of wire, wire sweep, filling time and void in package during the encapsulation process. The optimization of the PBGA encapsulation was carried out by considering the fluid/structure interaction (FSI) aspects. The optimum empirical models were examined and well confirmed with the simulation results. The optimum design of the PBGA package (30 mm × 30 mm) for both physical and process parameters was characterized by 8 wire bonds, 0.25 mm of vent thickness, 4.46 s of filling time and 2.52 % of void at the inlet condition of 10 MPa.
... Moreover, the Castro−Makosco viscosity model was employed to describe the polymerization and to model the viscosity of moulding compound. The Castro-Macosko model, which provides more reliable predictions on flow rheology had been used by Jong et al. [2], and Khor et al. [8] in their integrated circuits (IC) simulation. By considering Castro-Macosko models, molten EMC behaves more or less as Newtonian fluid with the change in viscosity being the non-Newtonian aspect during the encapsulation process. ...
... TABLE I summarizes the material properties of the EMC [6 and 13]. The boundary and initial conditions are as follows [8]: In the simulation, the PBGA is modelled as a 3-D finite volume grid. The dimension of the mould model is 30 mm × 30 mm × 1.17 mm. ...
... Moreover, the mould temperature is set as 175 °C, and 0.3 m/s of inlet velocity is applied during the encapsulation process. The simulation was performed on an Intel Core 2 Duo processor E7500, 2.93 GHz with 2 GB of RAM; it took around 12 hours in each case to complete the 14000 iterations using 0.001 s of time step size [8]. The commercial FEM based software ABAQUS is used in this study to calculate the wire deformation. ...
This paper presents the computational of two-way fluid structure interaction technique by using Mesh based Parallel Code Coupling Interface for the visualization of wiresweep in the electronics packaging. Polymer rheology models with Castro-Macosko model have been used in the fluid flow model and Volume of Fluid technique was applied to melt front tracking of the fluid. The numerical analysis used User-Defined Function to allow curing kinetic model. Wiresweep profiles and pressure distribution within the mold are presented. The numerical results of melt front patterns and filled volume were compared with the previous experimental results and found in good agreement.
... The applications of these computing software in IC encapsulation significantly enrich research and development in this field. Virtual modeling tools, such as PLICE-CAD [1], FLUENT [2], C-Mold [3,4], Moldex3D [5], Autodesk Moldflow [6], FORTRAN [7], and ANSYS [8], have been utilized in IC encapsulation research. The advanced development of commercial software has helped researchers and engineers reduce research cost and time. ...
... The preformed EMC is transferred from the pot to the cavity through the runner to encapsulate the IC structures (silicon chip, solder bump, wire bonding, lead frame, and paddle). This technique has been Nomenclature A 1 , A 2 pre-exponential factors (1/s) B exponential-fitted constant (Pa s) C 1 ,C 2 fitting constant (-) C P specific heat (J/kg-K) E 1 ,E 2 activation energies (K) E elastic modulus (GPa) F front advancement parameter (-) k 1 , k 2 rate parameters described by an Arrhenius temperature dependency (1/s) m 1 , m 2 constants for the reaction order (-) n power law index (-) p pressure (Pa) [1,2], thin profile small outline package (TSOP II 54 L LOC) [3,10], ball grid array package (BGA) [4], stacked-chip scale package (S-CSP) [7,11], mold array package (MAP) [12], molded underfill (MUF) [13], and pressurized flip chip encapsulation [14]. Encapsulant flow behavior is dependent on the material characteristics and process control and may be influenced by IC package design during the process. ...
... The preformed EMC is transferred from the pot to the cavity through the runner to encapsulate the IC structures (silicon chip, solder bump, wire bonding, lead frame, and paddle). This technique has been Nomenclature A 1 , A 2 pre-exponential factors (1/s) B exponential-fitted constant (Pa s) C 1 ,C 2 fitting constant (-) C P specific heat (J/kg-K) E 1 ,E 2 activation energies (K) E elastic modulus (GPa) F front advancement parameter (-) k 1 , k 2 rate parameters described by an Arrhenius temperature dependency (1/s) m 1 , m 2 constants for the reaction order (-) n power law index (-) p pressure (Pa) [1,2], thin profile small outline package (TSOP II 54 L LOC) [3,10], ball grid array package (BGA) [4], stacked-chip scale package (S-CSP) [7,11], mold array package (MAP) [12], molded underfill (MUF) [13], and pressurized flip chip encapsulation [14]. Encapsulant flow behavior is dependent on the material characteristics and process control and may be influenced by IC package design during the process. ...
... This procedure protects the IC package from hazardous situations, such as vibration, temperature effect, and moisture, from the environment. Therefore, encapsulation processes [4,5], such as thin-quad flat package [6,7], thin-profile small outline package (TSOP II 54 L LOC) [8,9], stacked-chip scale package [10], mould array package [11] and moulded underfill [12], have been widely applied in the microelectronic industry for IC packaging. During the process, the interaction between EMC and the structures causes deformation. ...
... In the actual-size packaging, the Castro-Macosko model with curing effect was used to describe the EMC fluid behaviour during the encapsulation process. This model was written into appropriate user-defined functions (UDFs) [7] and incorporated into the FLUENT analysis. The volume of fluid (VOF) method was applied to track the flow front. ...
... During the FSI modelling, the EMC fluid was assumed to be a generalized Newtonian fluid. The viscosity behaviour of EMC was expressed by the Castro-Macosko model [6,7,15,28] for predicting the relationship between viscosity and the degree of polymerization gðT; _ cÞ ¼ g 0 ðTÞ ...
... The appropriate selection of the viscosity model in simulation modelling is essential to obtain the optimum predictions of the EMC behaviour in the IC encapsulation process. Various viscosity models have been utilized by researchers, such as power law model [10], Cross viscosity model [11,12], Castro-Macosko model [13][14][15], and Herschel-Bulkley model [16]. According to our previous work [10], the application of a non-Newtonian power law model in IC encapsulation induced the unstable EMC flow front, hence causing the fluctuation phenomenon in the process. ...
... Moreover, the use of the Castro-Macosko model [17] was found to be more stable and provided reliable predictions on flow rheology compared with the power law and Cross model in the IC encapsulation. Therefore, the most suitable Castro-Macosko model is selected for the optimum predictions in the EMC flow, as this model has been widely used in IC encapsulation processes such as TQFP [13,14], S-CSP [11,17] and MUF [10,18]. This model considers the effect of chemical conversion of the compound that influences viscosity; hence, the realistic EMC flow front behaviour can be predicted during the IC encapsulation process. ...
... The EMC material was assumed as generalized Newtonian fluid (GNF). The Castro-Macosko model [13][14][15] was used to predict the relationship between the viscosity and degree of polymerization, and describe the viscosity of the EMC as follows: ...
Optimized design of the integrated circuit (IC) package gives better IC encapsulation process and minimizes the stress concentration and deformation of the IC structures. The physical and process parameters (i.e., pressure inlet, solder bump standoff height, chip thickness, gap-wise between chips, and mould and filled time) were optimized via response surface methodology using central composite design (CCD) to minimize the stress concentration of chip and solder bump, chip deformation, and void in package during the IC encapsulation process. The optimization of the moulded IC encapsulation is carried out by considering the fluid/structure interaction (FSI) aspects. The optimum empirical models were tested and well confirmed with the simulation results. The optimum design of the IC package (20 mm × 20 mm) with perimeter solder bump arrangement for both physical and process parameters was characterized by 150 μm of solder bump standoff height, 250 μm of chip thickness, and 50.43 μm of gap-wise at the inlet condition of 3.43 MPa.
... The numerical analysis uses userdefined functions to account for the curing kinetics. In this paper, the computational fluid dynamic code FLUENT 6.3 [19]- [21] is used to analyze the effect of rheology on the flow behavior and wire sweep of the encapsulation process of PBGAs. The 3-D models are developed and analyzed by using the finite volume method. ...
... In the simulation model, the encapsulation process material and air are assumed incompressible and the governing equations that described the fluid flow are those of the conservation of mass, momentum, and energy (refer to [19]). FLUENT nor- mally solves the governing equations using Cartesian spatial coordinates and velocity components as given below. ...
... The VOF model in FLUENT 6.3.26 is utilized to simulate the process [19]- [21]. EMC types are set at different parameters, as shown in Table I. ...
This paper presents a 3-D fluid–structure interaction (FSI) technique using mesh-based parallel code coupling interface (MpCCI) for the visualization of wire sweep during encapsulation of the plastic ball grid array packaging, considering the polymer rheology effect. In the molding process, the encapsulant flow behavior is modeled by the Castro-Macosko viscosity model including the curing effect and volume of fluid technique for melt-front tracking. The viscosity model is written in C language and compiled using user-defined functions into the FLUENT analysis. Wire sweep behavior is analyzed by ABAQUS and integrated with FLUENT software by MpCCI as an interface of fluid and solid interaction. Three types of epoxy molding compound (EMC), namely, Cases 1–3, were utilized for the study of fluid flow inside the mold cavity. The melt-front profiles and viscosity versus shear rate for all cases are analyzed and presented. The degree of conversion of the molding compound during the encapsulation process at the top view of the package for different EMCs is also studied. Pressure distribution around the wire region and wire sweep profiles within the mold are presented. The numerical results of the melt-front behavior and wire sweep are compared with the previous experimental results and found in good conformity. In the present case, Case 2 with a lower viscosity shows lower air trap, lower pressure distributions, and lower wire deformation. Therefore, the strength of MpCCI in handling FSI problems is proven to be excellent. The work presented in this paper is expected to be a reference and guide for the microelectronics industry.
... The encapsulant material was assumed to be a generalized Newtonian fluid. The Castro-Macosko model [1], [9], [22], [23] was used to predict the relationship between the viscosity and degree of polymerization and to describe the viscosity of the encapsulant material as follows: ...
... B is an exponential-fitted constant, T b is a temperature fittedconstant, n is the power law index, η o is the zero shear viscosity, and τ * is a parameter that describes the transition region between the zero shear rate and power law region of the viscosity curve. The curing effect described by the equation of Kamal [1], [9], [22], [23] was integrated with the Castro-Macosko model. Fig. 4. Solder bump geometries. ...
... Hence, predictions for the same problems could not be carried out. However, the prediction of the present methodology in the modeling of encapsulation and injection moulding has been well validated in our previous works [5], [22], [26]. The predictions of flow front advancement and viscosity variation well matched the experimental results. ...
This paper presents a fluid/structure interaction (FSI) analysis of the effects of solder bump shapes and input/output (I/O) counts on moulded packaging. The FSI events during the encapsulation process are investigated using a virtual modeling technique, whose mesh-based parallel code-coupling interface couples both finite volume and finite element codes. In this paper, the effects of five different solder bump shapes, denoted Cases 1–5, are considered in the perimeter and full array of solder bump arrangements with different I/O counts. The FSI between the epoxy moulding compound and structures (silicon chip and solder bumps) is presented in the displacement profile. The effects of the bump shape and I/O count are considered in the flow front advancement, structure displacement, stress, and void formation. The maximum displacements, von Mises stresses, and voids are minimized by implementing the bump shape in Case 3. The applications of Cases 3 and 5 with higher I/O counts (full array type) reduced the stress concentration in the solder bump by nearly 40% and 60%, respectively, compared to the cases with lower I/O counts (perimeter type). Index Terms— Finite element, finite volume, fluid/structure interaction, moulded package, void formation.
... However, the occurrence of void formation reduces package reliability during the encapsulation process. This problem was mentioned in various IC encapsulation processes, such as the thin quad flat package (TQFP) [3,4], TSOP II 54L LOC [5,6], stacked-chip scale package (S-CSP) [7][8][9][10], mold array package (MAP) [11], and molded underfill [12]. ...
... They also reported that the void size decreases with the increasing inlet flow rate. Khor et al. [4] used the finite volume method (FVM) to study the extension of the TQFP encapsulation and the FLUENT software to perform the simulation analysis. The utilization of the multi-gate inlet and the change in gap height in the TQFP design promise the reduction of filling time and minimization of the chances of void formation. ...
... In recent years, the computational modeling technique has been widely implemented in predicting and improving IC packaging. Modeling tools, such as PLICE-CAD [2], FORTRAN [7][8][9], FLUENT [4,10], C-MOLD [6,14], and Moldex3D [15], have been used for the continuous improvement of various types of IC packages. The commercial computer-aided engineering (CAE) and the finite elementbased software assist researchers in enhancing the deformation of wire bonding [16] and paddle shift [17,18] during the encapsulation process. ...
... In 3D IC integration, thinned silicon chips and micro-size interconnection require reliable housings to maintain the device's reliability and protect them from the hazardous environment. The encapsulation process [3, 4] using epoxy-moulding compound (EMC) was widely used for various IC packages such as thin quad flat packages (TQFPs) [5,6], thin profile small outline packages with wide side of lead on chip (TSOP II 54 L LOC) [7,8], stacking-chip scale packages [9], mould array packages [10] and moulded underfills [11]. During the encapsulation process, the EMC is fed into the cavity through transfer moulding to encapsulate structures such as the silicon chips, wire bondings, solder bumps, paddles and passive components. ...
... The various IC applications of TSV technology and the diverse applications of the encapsulation process in different packages were reported [3][4][5][6][7][8][9][10][11]. However, the investigation of the encapsulation process in 3D IC packages considering TSVs and structural analysis is still rarely reported in the literature. ...
... Factors that influence the package quality during the encapsulation process include package design, material selection and process control. The design of the physical characteristics of the IC package and moulding parameters, such as inlet and outlet gates, orientation of stacking chips, number of stacking chips, solder bump standoff height and package size, may affect the fluid flow, filling time and void formation in the encapsulation [6]. Improper selection of EMC materials [11] may also cause void formation, delamination and shrinkage of compound. ...
This paper presents the modelling and analysis of the encapsulation process for three-dimensional (3D) stacking-chip package with through-silicon via (TSV) integration. The fluid-structure interaction of the 3D stacking-chip package encapsulation was modelled by finite volume and finite element codes, which were solved separately. The effect of the increase in the number of stacking chips was analysed. The visualization of the 3D stacking-chip package encapsulation process was presented at different filling times. The void formation around the stacking chips was identified for each case. The displacement and von Mises stress for the copper through-silicon vias were determined. The use of designed inlet-outlet heights in the integrated circuit package maintained the filling time of the encapsulation process and reduced the void of the packages as the number of stacking chips increased. The encapsulation model facilitated a clear visualisation and enhanced fundamental understanding of the design of a 3D integrated circuit encapsulation. The proposed analysis is expected to be a reference and guide in the design and improvement of 3D integration packages. © 2012 by Maejo University, San Sai, Chiang Mai, 50290 Thailand.
... The encapsulant material was assumed to be a generalized Newtonian fluid. The Castro-Macosko model [1], [9], [22], [23] was used to predict the relationship between the viscosity and degree of polymerization and to describe the viscosity of the encapsulant material as follows: ...
... B is an exponential-fitted constant, T b is a temperature fittedconstant, n is the power law index, η o is the zero shear viscosity, and τ * is a parameter that describes the transition region between the zero shear rate and power law region of the viscosity curve. The curing effect described by the equation of Kamal [1], [9], [22], [23] was integrated with the Castro-Macosko model. Fig. 4. Solder bump geometries. ...
... Hence, predictions for the same problems could not be carried out. However, the prediction of the present methodology in the modeling of encapsulation and injection moulding has been well validated in our previous works [5], [22], [26]. The predictions of flow front advancement and viscosity variation well matched the experimental results. ...
This paper presents a fluid/structure interaction (FSI) analysis of the effects of solder bump shapes and input/output (I/O) counts on moulded packaging. The FSI events during the encapsulation process are investigated using a virtual modeling technique, whose mesh-based parallel code-coupling interface couples both finite volume and finite element codes. In this paper, the effects of five different solder bump shapes, denoted Cases 1-5, are considered in the perimeter and full array of solder bump arrangements with different I/O counts. The FSI between the epoxy moulding compound and structures (silicon chip and solder bumps) is presented in the displacement profile. The effects of the bump shape and I/O count are considered in the flow front advancement, structure displacement, stress, and void formation. The maximum displacements, von Mises stresses, and voids are minimized by implementing the bump shape in Case 3. The applications of Cases 3 and 5 with higher I/O counts (full array type) reduced the stress concentration in the solder bump by nearly 40% and 60%, respectively, compared to the cases with lower I/O counts (perimeter type). © 2012 IEEE.
... In 3D IC integration, thinned silicon chips and micro-size interconnection require reliable housings to maintain the device's reliability and protect them from the hazardous environment. The encapsulation process [3, 4] using epoxy-moulding compound (EMC) was widely used for various IC packages such as thin quad flat packages (TQFPs) [5,6], thin profile small outline packages with wide side of lead on chip (TSOP II 54 L LOC) [7,8], stacking-chip scale packages [9], mould array packages [10] and moulded underfills [11]. During the encapsulation process, the EMC is fed into the cavity through transfer moulding to encapsulate structures such as the silicon chips, wire bondings, solder bumps, paddles and passive components. ...
... The various IC applications of TSV technology and the diverse applications of the encapsulation process in different packages were reported [3][4][5][6][7][8][9][10][11]. However, the investigation of the encapsulation process in 3D IC packages considering TSVs and structural analysis is still rarely reported in the literature. ...
... Factors that influence the package quality during the encapsulation process include package design, material selection and process control. The design of the physical characteristics of the IC package and moulding parameters, such as inlet and outlet gates, orientation of stacking chips, number of stacking chips, solder bump standoff height and package size, may affect the fluid flow, filling time and void formation in the encapsulation [6]. Improper selection of EMC materials [11] may also cause void formation, delamination and shrinkage of compound. ...
This paper presents the modelling and analysis of the encapsulation process
for three-dimensional (3D) stacking-chip package with through-silicon via (TSV)
integration. The fluid-structure interaction of the 3D stacking-chip package encapsulation
was modelled by finite volume and finite element codes, which were solved separately.
The effect of the increase in the number of stacking chips was analysed. The visualisation
of the 3D stacking-chip package encapsulation process was presented at different filling
times. The void formation around the stacking chips was identified for each case. The
displacement and von Mises stress for the copper through-silicon vias were determined.
The use of designed inlet-outlet heights in the integrated circuit package maintained the
filling time of the encapsulation process and reduced the void of the packages as the
number of stacking chips increased. The encapsulation model facilitated a clear
visualisation and enhanced fundamental understanding of the design of a 3D integrated
circuit encapsulation. The proposed analysis is expected to be a reference and guide in
the design and improvement of 3D integration packages.
... Subsequently, the FVM-based ANSYS FLUENT software was introduced and applied for the modeling of underfill flow in various [17,18,[24][25][26], (b) microparticle image velocimetry experiment using transparent imitated chips [27,28], (c) mold underfill experiment using scaled-up imitated chips [29], and (d) capillary underfill experiment using scaled-up imitated chips [20,30] types of underfill process including conventional capillary [20,30,39,47,[54][55][56][57], mold [37,38,40,55,58,59], pressurized [11], and no-flow [60]. FVM simulation gives various data on the underfill flow, filling time, and flow's dynamic and thermal distributions. ...
... For mold underfill, the void occurrence decreases with the introduction of vacuum, while better vacuum quality gives smaller voids formed [14]. For mold underfill, typical inlet gate gives less void occurrent compared to both diagonal and top center inlet gates [40,58]. ...
Underfill encapsulation is a crucial manufacturing process in enhancing the reliability of flip-chip packaging, thus it remains an active research subject. This review work encompassed various literatures that focused on the underfilling stage of encapsulation process. Generally, the visualization analysis of underfill flow in the bump array is crucial for the filling time determination as well as the
predictions of void occurrence. Subsequently, the parametric design optimization was conducted to resolve the productivity issue of long filling time and reliability issue of void occurrence. Statistically, it was found that the conventional capillary is the most studied underfill process while the numerical simulation was mainly adopted. To enrich the design versatility and flow visualization aspects, experimental test vehicle was innovated using imitated chip and replacement fluid, or even being scaled-up. Additionally, the discretization scheme of numerical underfill study shifted from finite element method to finite volume method, for enhancing the flow prediction. Nonetheless, the analytical filling time models became more accurate and sophiscasted over the years, despite still being scarce in number. Overall, underfill researches could provide useful and practical guidelines to
the industries. With the technological advancement on analysis tools and further development of analytic skills, it was believed that the future researches on underfill flow will become more comprehensive, thereby leading to the production of better packages in terms of manufacturing feasibility, performances and reliability.
... For the settings in FLUENT, time dependent formulation and implicit solution were applied for the volume fraction at every time step. Optimum time step of 0.001s (Khor et al., 2011b;Ramdan et al., 2012a) was applied in the research. ...
... Void formation that leads to moldcap crack and ultimately chip crack(Braun et al., 2007) In thin quad flat package (TQFP),Khor et al. (2011b) studied on the implications of different inlet gates to the overall EMC flow and the air entrapment ...
Through-silicon via (TSV) technology has been an emerging technology to
3D heterogeneous system integration through vertical interconnection. This
promising technology enables smaller footprints, reduced signal delay, shorter
interconnections, lower power consumption and higher integration density as
compared to the existing 2D planar system integration and 3D IC with wire bonds.
Despite all the benefits, there are still many challenges ahead for this technology to
be both technically and economically viable. Plastic encapsulation process is one of
the critical challenges in the continual shrinking of TSV diameter, wafer thickness
and microbump pitch. In this thesis, both experimental and numerical approaches are
used to study the plastic encapsulation process in 3D IC package with TSV. The
objectives of this research include establishing feasible methods to analyze flow front
advancement, pressure distribution, velocity profile and curing rate of epoxy molding
compound during encapsulation process. Several parametric studies have been
presented, which include the implications of microbump pitch, microbump arrays,
EMC rheological properties and multi-stacked chips. Fluid/structural interaction
(FSI) is an important phenomenon occurred during the plastic encapsulation, which
is considered during the study. FLUENT 6.3 and ABAQUS 6.9 are used to compute
the fluid flow behaviors and structural dynamics respectively under the governing
equations and user-defined functions (UDF). MpCCI 3.1 is the coupling interface
used to compute the continuous interaction between fluid and structural domain. Through this coupling environment, the FSI activity can be visualized thoroughly,
which is very hard to visualize during the actual process if it is not impossible. From
the research, it was found that small microbump pitch, high density of microbump
array and high viscous flow of EMC are unfavorable in encapsulation process. High
air entrapment level is anticipated when one of these conditions is met. High stacking
chips could also trigger high displacement and high von Mises stress as observed in
the numerical study. The numerical approach used in the study has provided an
alternative route to parametric study prior to the actual experimental study, which
might involve higher cost in hardware modifications and higher time consumption.
Therefore, the findings in the thesis are valuable as it displays an effective approach
to predict FSI, and its effects to the delicate TSV structures during plastic
encapsulation process.
... Compound flow turning effect occurs at corner 2 (areas B and C) and corner 4 (areas F and G) whereby the mold gate is located at the top-left of the package, as shown in Fig. 5(b), which agrees with previous studies. 7,8,11 The 90 flow turning effect results in a higher impact and increased force to the wire trajectory and eventually yields the worst wire sweep performance. Epoxy molding compound is a type of thermoset polymer materials. ...
... However, the compound cure effect and degree of conversion leads to an increase in onset pressure (any location) for the entire mold cavity. 8 Furthermore, the statistical analysis was performed again to Fig. 1. The wire pitch was determined by measuring the distance between two wires, i.e., wire #N minus wire #(N-1), as shown in Fig. 1. ...
Transfer molding is the most effective method for molding encapsulation for semiconductor packaging due to low maintenance cost and high production yield. Wire sweep is a critical moldability issue as excessive wire sweep will contact neighbouring wires, causing electrical short that consequently leads to electrical failure of the package. Wire sweep characterization was carried out with various wire locations, mold flow directions, wire lengths, wire pitches and wire angles on Low Quad Flat Packages (LQFP). JMP statistical analysis was performed to determine the significant factors and correlations of wire sweep performance. It was found that wire length has the most significant correlation with wire sweep percentage. The four wires, two at the bottom-left and top-right (and hence designated as corner 2 and 4, respectively) exhibited the worst wire sweep when the mold gate was located at the top-left corner of the package. The wire sweep performance of seven wire layouts with varying wire lengths were also investigated. The results have revealed and proven that the two wires (corner 2 and 4, respectively) exhibited a higher wire sweep percentage. Overall, it was found that wire X4 has the highest wire sweep deflection.
... The IC encapsulation technology is widely used in the microelectronic industry for various types of IC packages, such as thin quad flat package [4], [5], thin-profile small outline package (54 L lead on chip) [6], [7], stacked-chip scale package [8], mold array package [9], molded underfill [10], and flip-chip underfill encapsulation [11]. During the encapsulation, the epoxy-molding compound (EMC) is transferred into the mold cavity using the transfer molding technique to protect the structures (silicon chip, solder bumps, lead frame, and wire bonding) from the hazardous environment (mechanical, chemical, thermal, etc.). ...
... Moreover, a larger void was found in the stacking-chip package, which was caused by the unstable flow front in the upper, middle, and lower streams during the filling process. Thus, applications of multi-inlet [5] and optimized inlet positions [10] could effectively eliminate the void formation in actual IC packaging. ...
... The IC encapsulation technology is widely used in the microelectronic industry for various types of IC packages, such as thin quad flat package [4], [5], thin-profile small outline package (54 L lead on chip) [6], [7], stacked-chip scale package [8], mold array package [9], molded underfill [10], and flip-chip underfill encapsulation [11]. During the encapsulation, the epoxy-molding compound (EMC) is transferred into the mold cavity using the transfer molding technique to protect the structures (silicon chip, solder bumps, lead frame, and wire bonding) from the hazardous environment (mechanical, chemical, thermal, etc.). ...
... Moreover, a larger void was found in the stacking-chip package, which was caused by the unstable flow front in the upper, middle, and lower streams during the filling process. Thus, applications of multi-inlet [5] and optimized inlet positions [10] could effectively eliminate the void formation in actual IC packaging. ...
This paper presents the visualization of the fluid/structure interaction (FSI) in molded integrated-circuit (IC) packaging. The complexity and high cost of the experimental setup in the molded packaging make the FSI visualization difficult during the encapsulation process, particularly for tiny and thinned chips in IC packages. To address this problem, we fabricated a scaled-up transparent molded package, and the encapsulation process was experimentally performed to visualize the FSI phenomenon. Two scaled-up (single{-} and stacked-chip) IC packages were considered in the experiment to investigate the FSI, flow front advancement, and void formation. The void formation mechanisms for both imitated IC packages were also studied. Moreover, finite-volume and finite-element codes, via the mesh-based parallel code coupling interface method, were used to describe the physics of FSI during the encapsulation. The predicted flow front advancement, flow profiles, and chip deformation were validated with the experimental results. Hence, this paper is expected to provide a better understanding of the FSI phenomenon during the IC encapsulation.
... EMC was assumed to be a generalised Newtonian fluid (GNF). The viscosity behaviour of EMC was described by the Castro-Macosko model [10,17,24,25] for predicting the relationship between viscosity and the degree of polymerisation, which is expressed as follows: ...
... where B is an exponential-fitted constant, T b is a temperature fittedconstant, n is the power law index, g 0 is the zero-shear viscosity, and s à is the parameter that describes the transition region between zero-shear rate and the power law region of the viscosity curve. The Kamal's equation [10,17,24,25] is integrated with the Castro-Macosko model in this study. The rate of chemical conversion of the compound is predicted as follows: where a is the conversion, A 1 and A 2 are Arrhenius pre-exponential factors, E 1 and E 2 are the activation energies, m and n are the reaction orders, and T is the absolute temperature. ...
In the present study, experiment and simulation studies were conducted on the fluid/structure interaction (FSI) analysis of integrated circuit (IC) packaging. The visualisation of FSI phenomenon in the actual package is difficult due to limitations of package size, available equipment, and the high cost of the experimental setup. However, the experimental data are necessary to validate the simulation results in the FSI analysis of IC packaging. Scaled-up package size was fabricated to emulate the encapsulation of IC packaging and to study the effects of FSI phenomenon in the moulded package. The interaction between the fluid and the structure was observed. The deformation of the imitated chip was studied experimentally. The air-trap mechanism that occurred during the experiment is also presented in this paper. Simulation technique was utilised to validate the experimental result and to describe the physics of FSI. The predicted flow front was validated well by the experiment. Hence, the virtual modelling technique was proven to be excellent in handling this problem. The study also extends FSI modelling in actual-size packaging.
... x-x, 2017. could cause by the number of inlets and outlets (Khor et al., 2011). Consequently, the optimized design and position of the inlet gate could effectively minimize the void formation and enhance the package reliability. ...
The fluid/structure interaction (FSI) investigations of stacked chip in encapsulation process of moulded underfill packaging using the two-way Coupling method with ANSYS Fluent and ANSYS Structural solvers are presented. The FSI study is executed with different aspect ratio of stacked chip on the mould filling during the encapsulation process. The simulation results in the FSI study is well validated with experimental setup. The epoxy moulding compound (EMC) and structure (chip) interaction is analyzed for better understanding the FSI phenomenon.Von Mises stresses experienced by the chip also be monitored for risk of chip cracking. The proposed analysis is anticipated to be a recommendation in the chip design and improvement of 3D integration packages.
... There are already few researches on fluid flow simulation through BGA in the past but they are mainly focused on finite volume method (FVM) and finite element method (FEM) [13].However, the FVM and FEM are limited to macro-scale level only. The LBM uses a simplified kinetic equation for simulating fluid flow. ...
This paper reports on the enhancement of the heat transfer in high power LEDs by a combination of piezoelectric fans and a heat sink. Experimental and numerical studies were conducted to evaluate the heat dissipation efficiency of the package of high power LEDs operating under multiple vibrating fans. Dual and quadruple vibrating fans were vertically positioned to a finned heat sink embedded in the LEDs package. Thermal resistance is observed to be sensitive to the separation distance between the two vibrating fans in array at their respective heat sink slots. Thermal resistance (R), the junction temperature (TJ), and the average heat transfer coefficient ( ) were estimated. A substantial reduction of the thermal resistance was observed at intermediate P/Apf = 7 separation distance at three different heating powers (Q). The computed results revealed that the dual fans enhanced the heat transfer performance by approximately 3.2 times, while the quadruple fans enhanced heat sink of the LEDs by 3.8 times compared to natural convection.
... There are already few researches on fluid flow simulation through BGA in the past but they are mainly focused on finite volume method (FVM) and finite element method (FEM) [13].However, the FVM and FEM are limited to macro-scale level only. The LBM uses a simplified kinetic equation for simulating fluid flow. ...
The current study applied the lattice Boltzmann method to examine the effects of stacking chips layout to the micro-void formation in three-dimensional (3D) packaging. Three-dimensional 19-velocities commonly known as D3Q19 scheme is utilized in this study. Three different cases, which are different in layout design, are examined. For code verification purpose, an experimental work is also presented to compare the flow front results between numerical and experimental at different filling percentage. The numerical predictions compared well with the experimental results. Minor differences are observed in their flow front profile. The numerical findings identified the predicted locations of micro-void formation during the encapsulation process. The entrapment of micro-void was visualized clearly in the simulation because of the unbalanced molecular force at the interface during encapsulation. Knit lines were also identified at the interface between the flows that occurred in the encapsulation. Different layout of stacking flip-chips package have influence the micro-void in the package, which tended to form at the stacking chips region. The results show that the lattice Boltzmann method has a good performance in the IC encapsulation simulation.
... Currently, most of the researches on POP are mainly simulated using FVM based software in which is based on macroscale formulation. C.Y. Khor et al. ( , 2013 have conducted three different studies using ANSYS on the ball grid array (BGA) package encapsulation process by considering three different parameters which is inlet pressure, silicon chip thickness and solder bump arrangement [4,20,21]. C.Y. highlights the importance of inlet pressure parameter on FSI of BGA package encapsulation. The FSI analysis is conducted by using Mesh-based parallel Code Coupling Interface (MpCCI) method with finite volume coding (FLUENT) and finite element coding (ABAQUS). ...
This paper studies the three dimensional (3D) simulation of fluid flows through the ball grid array (BGA) to replicate the real underfill encapsulation process. The effect of different solder bump arrangements of BGA on the flow front, pressure and velocity of the fluid is investigated. The flow front, pressure and velocity for different time intervals are determined and analyzed for potential problems relating to solder bump damage. The simulation results from Lattice Boltzmann Method (LBM) code will be validated with experimental findings as well as the conventional Finite Volume Method (FVM) code to ensure highly accurate simulation setup. Based on the findings, good agreement can be seen between LBM and FVM simulations as well as the experimental observations. It was shown that only LBM is capable of capturing the micro-voids formation. This study also shows an increasing trend in fluid filling time for BGA with perimeter, middle empty and full orientations. The perimeter orientation has a higher pressure fluid at the middle region of BGA surface compared to middle empty and full orientation. This research would shed new light for a highly accurate simulation of encapsulation process using LBM and help to further increase the reliability of the package produced.
... To the knowledge of the authors, no papers have been published that utilize LBM to solve and predict void formation problem. There are already few researches on fluid flow simulation through BGA in the past but they are mainly focused on finite volume method (FVM) and finite element method (FEM) [10]. A review on comparison between LBM and FVM proves the capability of another fluid flow simulation method which is LBM for BGA evaluation since LBM provides same accuracy as FVM on fluid flow simulation and better capability in dealing with instantaneous flows. ...
... Hence, the molten polymer molding compound can be treated as a shear-thinning generalized Newtonian fluid. The Castro-Macosko model [6,7] as shown in equation (1) is used to simulate the viscosity of the molding compound. This is the most commonly used viscosity model for such polymer materials. ...
The rapidly increasing demand of embedded wafer level package (EMWLP) due to its advantages, smaller form factor and flexibility in system level integration leads to the development of reconstructed wafer level encapsulation. The reconstructed wafers are encapsulated with epoxy molding compound using compression molding. Due to EMWLP advanced applications, there is a need to use multi chips with different layout in a single package. The overall reconstructed wafer design then became complex that eventually leads to asymmetrical chips layout within the wafer. One major challenge in molding of reconstructed wafer with multi-chip layout was the incomplete filling due to imbalance mold compound flow during compression molding. This study was conducted to determine the actual mold compound flow during compression molding of EMWLP with multi chips layout. Mold flow studies has been carried out on different multi-chip layouts using ANSYS Poly flow/Fluent software and results revealed that asymmetrical chips layout had imbalance mold flow response. The result of the mold flow simulation was then compared to the actual mold compound flow during compression molding by performing intentional short shots at different mold filling stages. It was confirmed that actual molding with asymmetrical chips layout also resulted to unbalance mold filling. The flow of the molding compound in areas with wider gaps was faster compared to areas with narrow gaps. This suggests that the chips layout determines the actual mold compound flow during compression molding. Balanced mold compound flow was achieved by re-arranging the chips into a symmetrical layout. In addition, this paper also shows that by changing the dispensing pattern to oval shape, the actual mold compound flow on asymmetrical chips layout became balanced. The mold flow simulation results with different chips layout were validated with experimental mold compound flow tests. The simulation and experimental results revealed that - he chips layout and mold compound materials dispensing pattern are critical to achieve excellent molding quality results.
... Hence, the molten polymer molding compound can be treated as a shear-thinning generalized Newtonian fluid. The Castro-Macosko model [9], [10], as shown in (1), is used to simulate the viscosity of the molding compound. This is the most commonly used viscosity model for such polymer materials. ...
This paper focuses on the 3-D numerical methodology development of wafer level compression molding. With its successful application in a two-die-package embedded wafer level encapsulation, flow patterns, velocity, and pressure distributions are compared for different die size and die thickness. The computed flow-induced forces indicate which zone has a high risk of die sliding. The simulated molten molding compound flow fronts are compared with actual molding short shot samples. The key advantage of this numerical study is that it helps detect the molding defects quickly and improve moldability problems efficiently, in order to reduce manufacturing cost and design cycle time.
... Thus, the soldering pot was defined with solder material (volume fraction, F = 1) in the simulation. The flow motion of the molten solder was described by the governing equations (i.e., conservation of mass, momentum, and energy) [10]. ...
... Thus, the soldering pot was defined with solder material (volume fraction, F = 1) in the simulation. The flow motion of the molten solder was described by the governing equations (i.e., conservation of mass, momentum, and energy) [10]. ...
This paper presents the three-dimensional finite-volume-based simulation of the effects of pin through-hole (PTH) offset position in a wave soldering process. The PTH model was built and meshed by using GAMBIT software and tetrahedral/hybrid elements. In the wave soldering process, the advancement of molten solder was tracked by using Volume of Fluid technique. FLUENT software was employed to analyze the filling of molten solder (63Sn37Pb) and the capillary action between printed circuit board (PCB) and PTH connector. The effects of five offset positions (i.e., cases I to V) for a single PTH connector through PCB were investigated in the simulation study. The PTH offset position revealed significant influences on the filling time and profile. The increase of offset position resulted in a decrease of filling time and encouraged an uneven solder profile. Predicted solder profiles were substantiated by the experimental results, demonstrating the excellent capability of the current simulation model to handle the PTH filling problem.
... Second-order upwind scheme and SIMPLE algorithm were used in the FLUENT setting. Inlet pressure was set at 2 MPa, and an optimum time step of 0.001 s was applied [22]. User-defined functions that define the viscosity and curing effect of EME 6300HN [23] were written in MS Visual Studio 2008 and integrated into FLUENT. ...
... However, as we only consider the compression stage, the flow pattern is not significantly affected by the elastic effects. The common practice is to use the Castro-Macosko model (Eq.1) to simulate the viscosity of the polymer molding compound [8,9]. The physical meanings of the corresponding coefficients are listed in Table 3: ...
This paper presents a new numerical model to characterize the compression molding of wafer level packaging with epoxy polymer molding compound. With its successful application on a reconfigured carrier wafer with fully populated 3-die packages embedded, flow pattern in the wafer level compression molding is characterized for various process conditions and 2 different molding compounds. Focuses have been given on die shift induced by the impact of compression mold flow. Flow pattern and flow drag on individual die is presented. If the adhesive force is less than the maximum flow drag on the die during compression molding, die shift will take place. Results show that the peripheral dies experience highest flow drag and thus are more likely to shift outwards. Moreover, higher compression speed at low molding temperature for a low viscosity molding compound increases the risk of die shift. Key advantage of this numerical study is to give the insights into process parameters and provide initial process window to prevent die shift induced by compression flow drag.
... Recently, Khor et al. [12] studied the effect of inlet gate arrangement on the filling time during TQFP encapsulation. A 3D model of plastic TQFP packages was built using GAMBIT and simulated by FLU-ENT software. ...
... Thus, F takes the value of 1 (F = 1) in cells that contains only resin, the value 0 (F = 0) in cells that are void of the resin, and a value between 0 and 1 (0< F <1) in "interface" cells or what are referred to as the "resin melt front." The equation of the melt front over time is governed by the following transport equation [18]: ...
This paper presents experimental and simulation studies of 3-D fluid/structure interaction (FSI) of wire sweep during the encapsulation process of plastic ball grid array (PBGA) packaging in different dies (single and stacked dies). A scaled-up package is fabricated to emulate the encapsulation of PBGA packaging and to study the effects of the FSI phenomenon in the PBGA package. A 3-D model of the mold and wires is created using GAMBIT, and the FSI is simulated using FLUENT and ABAQUS software integrated with mesh-based parallel code coupling interface for the real-time calculations. The effects of the stacked die and inlet pressure of the mold cavity on the melt flow behavior and wire sweep are mainly studied. A constant viscosity of the test fluid is assumed for the experiment. The volume-of-fluid technique is applied for melt-front tracking in the analysis. The numerical results of melt-front patterns and wire sweep are compared with the experimental results and good conformity is found. It is observed that the stacked die significantly influences the melt-front profile and the eventual wire sweep; as the number of dies in the stack increases, the wire sweep also increases.
... Kamal curing model was applied for modeling the EMC curing rate. Many scholars [9][10][11][12][16][17][18] have used these viscosity and curing models in predicting the encapsulation process of electronic packaging. The equations of Kamal curing model can be expressed as ...
This paper presented the study of encapsulation process in 3D stacked chips with different microbump arrays. An experiment was carried out on two-stacked chips with bumps in perimeter array, and validated with numerical simulation done in FLUENT 6.3. In the numerical study, three different microbump arrays, namely full, semi-full and perimeter arrays, were studied. It was found that perimeter array provided the easiest route for epoxy molding compound (EMC) flow front advancement with the least EMC conversion and microbump impediment. Therefore, the air entrapment level was the lowest in perimeter array. For full and semi-full arrays, higher level of air entrapment was observed as there were more significant EMC conversion, microbump impediment and imbalanced EMC flow fronts. The data presentation in this paper provides a good understanding on EMC flow behavior, especially in various microbump arrays during the encapsulation process.
... Moreover, the number of inlets and outlets also could cause the variation in the cavity pressure and influence the void formation in the encapsulation [25]. The optimized design and position of the inlet gate [9] could effectively minimize the void formation and enhance the package reliability. ...
This paper presents the computational study of fluid/structure interaction (FSI) analysis in the molding process using the Mesh-based parallel Code Coupling Interface (MpCCI) method with finite volume coding (FLUENT 6.3) and finite element coding (ABAQUS 6.9). The FSI analysis is implemented on the molded package during the encapsulation process with different inlet pressures. Real-time flow visualization, deformation and stress of the silicon die during the encapsulation process are presented in this paper. A fluctuation phenomenon of the silicon die is found in the encapsulation process when the inlet pressure increases. The maximum deformation during the process is determined at different locations on the silicon die, calculated during the final stage of the filling process. The deformation and stress of the die is exponentially increased with increasing inlet pressure. The maximum stress on the solder bump is concentrated near to the inlet gate. Thus, the present FSI analysis approach is expected to be a guideline or reference and provides better understanding of the encapsulation process for package design in the microelectronic industry.
... However, as we only consider the compression stage, the flow pattern is not significantly affected by the elastic effects. The common practice is to use the Castro-Macosko model (Eq.1) to simulate the viscosity of the polymer molding compound [8,9]. The physical meanings of the corresponding coefficients are listed in Table 3: ...
Through-silicon-via (TSV) technology permits devices to be placed and wired in the third dimension. Currently, there is a strong motivation for the semiconductor industry to move to 3-D integration using the TSV approach due to many advantages of TSV application. However, there are also some challenges for stacked die package with TSVs. One of the challenges is thermo-mechanical reliability of multi-layer stacked chip modules when subjected to temperature cycling loading. In this paper, multi-layer stacked chip modules with 6 via-last memory chips and one via-middle logic chip were investigated in terms of thermo-mechanical reliability using finite element modeling and simulation method in the design stage for packaging material selection, solder joint layout design, package size effect on reliability, and solder joint fatigue life assessment and so on. The simulation results show that underfill is one of the most important parameters relating to solder joint thermal fatigue life. The effect of underfill glass transition temperature (Tg) and coefficient of thermal expansion (CTE) on solder joint life is significant. High Tg and low CTE underfill results in high solder joint life. Substrate CTE is another key parameter in terms of solder joint thermo-mechanical reliability. When underfill with low Tg is used in package, package with low CTE substrate results in high solder joint life. However, when high Tg underfill is used in package, the effect of substrate CTE on solder joint is not significant. In addition, the effects of following parameters on solder joint reliability have also been investigated: solder joint layout design of peripheral vs. full array, solder joint alloy (low Ag vs. high Ag content solder), mold compound (molding height, mold compound material properties), substrate thickness, TSV and die thickness effects.
This study discussed the optimization of heat sink design parameters such as thickness, height and number of pin fins with the responses such as Nusselt Number, Nu and heat transfer coefficient, h to evaluate the rate of heat transfer with Response Surface Method (RSM). The evaluation of heat sink design parameters are important to ensure the capability and suitability for various applications. Besides, heat sink can be malfunction easily when experience high temperature for a long period of time due to its poor thermal management. The aim of this study is to analyze the performance heat sink for high temperature application in term of Nusselt numbers and heat transfer coefficient by using CFD simulation based optimization analysis and evaluate interaction relationship between heat sink parameters which are able to provide the best performance at high temperature application. At this optimization stage, an optimum values of height, thickness and number of pin fin were 41mm, 3mm and 10 respectively were generated maximum values of 375.97 Nusselt number and 9.10 W/m2℃ Heat transfer coefficient. Overall, the percentage error from both validation ways were consider as acceptable since its were less than 10.14% (Aghbolaghy and Karimi, 2013). Therefore, this finding from this study can be concluded a reliable results and better understanding of an interaction relationship between all these three design parameters in this Response surface methodology, optimization.
Solder joint is the important part in surface mount technology. The real time thermal stress, strain and displacement of the solder joint is difficult to observe and assess. To solve these problems, simulation analysis able to provide some information such as the thermal stress, strain and displacement. Thus, simulation tool ABAQUS software is used to solve the problem. By using Solidworks, model of leadless package was created. By using ABAQUS, thermal analyses were performed among four parameters which are solder length, solder width, solder height and thickness of PCB and obtain the results from the simulation analysis. By using this method, the real time thermal stress, strain and displacement of the solder joint can be obtained and assessed. After analyse the results, the change of size of solder and thickness of PCB just have minor effect to the strain. Change in solder length will have bigger effect to the stress while change in solder width just have minor effect to the displacement. Among the parameters, solder length has the biggest effect to the stress and displacement. So, factor solder length should be pay close attention by engineer or IC package designer. Change of PCB thickness and solder height will just have bigger effect to displacement while change of solder width will have bigger effect to the stress.
The purpose of this study was to investigate the injection molding parameters such as injection time, melt temperature, packing time and injection pressure. The aims for this study were to determine the capability of the injection molding parameter and to determine the behaviour of the ABS on these parameters. The material Acrylonitrile Butadiene Styrene (ABS) is used for this studied. Taguchi's L9 orthogonal array design was employed for the experimental plan. The parameters were rearranged as the orthogonal array, L9 by using the design expert and the effect of these parameters were determine using the analysis of variances (ANOVA). The finding form this study, the most significance factors will be determined for the injection molding process.
This research focuses on developing high-fidelity experimental and numerical models to analyze microscale underfill dynamics and void formation in high-density flip-chip packaging. Three underfilling scenarios are investigated, namely, point type, I-shaped line type, and L-type line type. The point-type underfilling validates the numerical model against experimental results, while the I-shaped and L-type line-type underfilling explore grid independence, void formation, and critical parameters such as filling position, contact angle, and liquid viscosity. Results indicate that contact angle and viscosity significantly influence filling efficiency and interface evolution. A smaller contact angle accelerates the process, reducing interface jumping motions. Viscous effects are quantified, revealing dimensionless filling time convergence. The use of low-viscosity surrogate fluids enhances numerical simulation efficiency. Sub-bump-sized, bump-sized, and sup-bump-sized voids are observed, identifying three void formation scenarios representing different underfilling flow mechanisms. This study provides insight into microscale flip-chip underfill physics and establishes validated models for next-generation high-density flip-chip products. These models can be further refined and integrated into optimization tools for automated process design, contributing to improved assembly yield and reliability of emerging electronic packages through physics-based understanding and modeling.
Purpose
The purpose of this study is to investigate the effect of the adhesive force and density ratio using lattice Boltzmann method (LBM) during underfill process.
Design/methodology/approach
To deal with complex flow in underfill process, a framework is proposed to improve the lattice Boltzmann equation. The fluid flows with different density ratio and bump arrangement in underfill are simulated by the incorporated Carnahan–Starling (CS) equation of state (EOS). The numerical study conducted by finite volume method (FVM) and experimental results are also presented in each case at the different filling percentage for verification and validation purpose.
Findings
The numerical result is compared well with those acquired experimentally. Small discrepancy is detected in their flow profile. It was found that the adhesive force between fluid and solid was affected by the density ratio of the fluids and solder bump configuration. LBM has shown better adhesive force effect phenomenon on underfill process compared to FVM. LBM also demonstrated as a better tool to study the fluid flow in the underfill process.
Practical implications
This study provides a basis and insights into the impact of adhesive force and density ratio to the underfill process that will be advancing the future design of flip chip package. This study also provides superior guidelines, and the knowledge of how adhesive force is affected by flip chip package structure.
Originality/value
This study proposes the method to predict the adhesive force and density ratio effect for underfill flow in flip chip package. In addition, the proposed method has a good performance in representing the adhesive force during the underfill simulation for its natural physical basic. This study develops understanding of flow problems to attain high reliability for electronic assemblies.
In the customary underfill (CUF) epitome process, there are couple of downsides experienced for instance, extended filling time, divided filling and voids improvement. Test and FVM reenactments have been directed to examine CUF dispensing systems for different types of ball grid array (BGA) tendencies out of a solitary layered PCB. In this task, the principle point is to enhance the stream of under filling mold crosswise over multi-stacks BGA. Package on Package (PoP), a strategy for coordinated circuit bundling, is utilized to consolidate BGA bundles vertically to permit higher segment thickness in devices. The L-type liquid stream in multi-stack BGA with edge introduction is contemplated and parameters of CUP exemplification, for example, void development and filling time were examined. The results demonstrated that the BGA sizes with the little weld balls put at the base layer, trailed by the medium size bind balls in the center stack and the biggest patch balls at the top layer has appeared to enhance the stream rate of the encapsulant ideally. Other arrangement in which the medium size solders placed are at the base layer, small solders at the center layer and largest solders on top of it, requires longest total filling time. The result also shows that the racing effect is present at central region and at the side of the layer. Because of the perimeter orientation design, the void formation is minimal and the race effect is not affecting much according experimental and computational result. This investigation additionally uncovers the capability of air gaps in improving velocity and pressure distribution near inlet and outlet to achieve faster total filling time at all layers of the BGA.
A comprehensive survey of the literature in the area of numerical heat transfer (NHT) published in 2010 and 2011 has been conducted. Journals surveyed in this article include Numerical Heat Transfer A and B, ASME Journal of Heat Transfer, International Journal of Heat and Mass Transfer, and International Journal for Numerical Methods in Fluids. The literature related to the topic of thermal rectifiers has been reviewed and included in the survey. A significant objective of this survey is to reduce the gap between the education and research communities. The survey presents a simple daily-life example with numbers to demonstrate how to extract the maximum work out from a can of Coke at 5C placed in a room at 27C. All articles are arranged and numbered according to last names of leading authors alphabetically and are organized into two categories, such as Science, Technology, and Engineering, and Math, Algorithms, Simulations, and Coding.
In this paper, the microbump pitch effect in molded underfill (MUF) is analyzed in the 3D integrated circuit (IC) package with a through-silicon via by numerical modeling. The current trend of decreasing the microbump pitch could make the MUF process more difficult. However, no detailed study on the particular area, particularly on the MUF process, has been conducted so far. Therefore, this paper could be a good reference by providing detailed information on the process. In our analysis, FLUENT 6.3.26 is used to predict the MUF flow front advancement under the effect of a different microbump pitch. The strong ability of FLUENT to predict flow front advancement was validated by the experimental results in the literature. Based on the analysis, the effect of the microbump pitch has significant implications on the filling rate, velocity profile, epoxy molding compound conversion rate, pressure distribution, and air void entrapment level. From the numerical analysis, a smaller microbump pitch is inferior in terms of the filling rate and air void entrapment level. The data and the analysis provide fundamental knowledge in understanding the effect of the microbump pitch on the MUF process.
In current study, simulation analysis was conducted to investigate the
fluid/structure interaction (FSI) phenomenon in two, three, and four
stacking chips package with through silicon via (TSV) during
encapsulation process. In actual packaging, the visualization of FSI
phenomenon is very hard due to the package size limitation, low
availability of suitable equipment, and high experimental setup cost.
Thus, modeling software such as FLUENT and ABAQUS were used
to predict the fluid flow and structural deformation during the
encapsulation process. Imitated package with scaled dimension were
modeled using both finite volume and finite element code, coupled
with MPCCI to perform the FSI analysis. The effects of increase in
stacking chips number were investigated. All the three cases showed
a similar mould filling rate using the designed inlet and outlet
dimension. Moreover, void formation was also successfully reduced.
Maximum von Mises stress and maximum displacement on
perimeter of silicon chips and structure of TSV and solder bump
were also determined. Larger chip displacement was observed at the
edge compared to the corner of the chip. For two and four stacked
chips package, the largest displacement of TSV and solder bumps
structure occurred at the highest point of the structure while largest
displacement occurred at the interface between the highest chip and
its subsequent chip for three stacked chip package. The simulation
model enhanced the understanding of FSI for stacked chip package
during encapsulation process by providing better visualization and
realistic prediction.
The 10×10 power TQFP is developed to meet the demand for low profile and high thermal performance. The SGS-Thomson package uses a conventional copper lead-frame combined with a drop-in copper heat slug. Since the power package shares the production line with standard TQFP's, its cost is kept low. The thermal performance is significantly improved by the copper slug. In steady state applications, the power TQFP is capable of dissipating 45% more power compared to the standard version. When the slug is soldered to the PC board during surface mounting, 55% more heat can be handled by the power package. In transient applications, the power TQFP can dissipate 30% and 80% more heat than the standard TQFP when the package is mounted to the PC board in a normal fashion and when the slug is directly soldered to the PC board, respectively.
Due to the increasing market demand for light-weight, high-performance ICs for portable information terminals, PHS (Personal Handy Phone System), electronic notebook, etc., the profiles of semiconductor packages for microprocessors and memories are being modified towards thinner body, fine-pitch, and higher pin-counts packages. Thinner packages require new technology to cope with various molding problems such as wire sway, cracking, voids, warpage, etc. This paper describes the features of the newly developed Compact Full Auto-Molding System (FAMS-C) especially designed for molding thin plastic IC packages such as 1.4 mm thickness LQFP (Low Profile Quad Flat Package) and 1 mm thickness TQFP (Thin Quad Flat Package) and TSOP (Thin Small Outline Package). An innovative pressurizing mechanism and injection mechanism have been devised by incorporating an electric servo motor instead of hydraulic oil cylinder, to realize a flexible, clean, high-throughput and floor-space saving advanced IC package molding system.
Electronics are used in a wide range of applications including computing, communication, biomedical, automotive, military and aerospace. They must operate in varying temperature and humidity environments including indoor controlled conditions and outdoor climate changes. Moisture, ionic contamination, heat, radiation and mechanical stresses are all highly detrimental to electronic devices and can lead to device failures. Therefore, it is essential that the electronic devices be packaged for protection from their intended environments, as well as to provide handling, assembly, electrical and thermal considerations. Currently, more than 99% of microelectronic devices are plastic encapsulated..
A non-contact infrared detection by a steady direct current electro-thermal technique is established to detect possible defects in electronic packaging. In the infrared detection process, researchers generally use the temperature rise attributed to the direct current source to estimate defects roughly. To detect defects accurately, the interference to the temperature rise due to parameters aside from defects (such as current inputs, defect types) needs to be filtered out. The so-called "temperature defect influence factor Theta" (i.e. the ratio of temperature rise of a defective structure detected from experiment to that of a perfect one from finite element analysis) together with a rigorous detection criterion are thus devised in this work to detect defects. By depicting the contours of the temperature defect influence factor, the shape, size, number and location of defects in electronic packaging can be clearly detected using the detection procedure developed. As a case study, the detection of defects in thin quad flat package (TQFP) is performed. The results demonstrate that the present technique is feasible and effective for defect detection in electronic packaging.
After encapsulation, thermomechanical deformation builds up within the electronic packages due to the temperature coefficient of expansion mismatch between the respective materials within the package as it cools to room temperature. At the same time, the chemical cure shrinkage exerts important influence on the total deformation. Due to the complexity and time consuming of the calculation, it is almost impossible for an industry to carry out the numerical simulation using viscoelastic property, which is the most close to the real material property of polymer material. However, finite element analysis (FEA) using temperature-dependent elastic property, temperature-dependent thermal expansion coefficient, and accurate chemical cure shrinkage can help to improve the accuracy on the stress and warpage prediction. This study has developed an evaluation method for the chemical cure shrinkage based on the measurement of the warpage of bimaterial model. The results show that FEA simulations without chemical cure shrinkage fail to accurately predict the package warpage. On the other hand, FEA simulations with chemical cure shrinkage are outlined, which show fair agreement with experimental measurements of package warpage over a range of temperatures. Furthermore, this study has evaluated the effect of silica filler percentage on the chemical cure shrinkage and confirmed that the chemical cure shrinkage decreases with the increase in silica filler percentage.
The plastic packaging process for integrated circuits is subject to several fabrication defects. For packages containing leadframes, three major defects may occur in the molding process alone, namely, incomplete filling and void formation, wire sweep, and paddle shift. Paddle shift is the deflection of the leadframe pad and die. Excessive paddle shift reduces the encapsulation protection for the components and may result in failures due to excessive wire sweep. Computer-aided analysis is one of the tools that could be used to simulate and predict the occurrence of such molding-process-induced defects, even prior to the commencement of mass production of a component. This paper presents a methodology for computational modeling and prediction of paddle shift during the molding process. The methodology is based on modeling the flow of the polymer melt around the leadframe and paddle during the filling process, and extracting the pressure loading induced by the flow on the paddle. The pressure loading at different times during the filling process is then supplied to a three-dimensional, static, structural analysis module to determine the corresponding paddle deflections at those times. The paper outlines the procedures used to define the relevant geometries and to generate the meshes in the "fluid" and "structural" subdomains, and to ensure the compatibility of these meshes for the transfer of pressure loadings. Results are shown for a full paddle shift simulation. The effect on the overall model performance of different element types for the mold-filling analysis and the structural analysis is also investigated and discussed. In order to obtain more accurate results and in a shorter computational time for the combined (fluid and structural) paddle shift analysis, it was found that higher-order elements, such as hexahedra or prisms, are more suitable than tetrahedra.
Paddle shift is one of the most serious defects which may arise during the IC encapsulation of leadframe-type packages. The term “paddle shift” means the deflection of the leadframe-pad and die as a result of the pressure difference between the top and bottom mold cavities. In extreme cases, paddle shift could lead to a substantial reduction in the reliability of package.This paper employed a computational approach to predict the paddle shift quantity during the IC packaging process. The approach was based on precise finite element (FE) models and flow-structure decoupled analyses. Two kinds of FE models were needed for the decoupled analyses, namely a 3D FE model for the mold filling analysis (i.e. fluid-flow mesh) and a 3D FE model for the structural analysis (i.e. paddle mesh). The aim of the mold filling analysis was to identify the pressure distribution acting on the paddle structure during the encapsulation process, while the objective of the structural analysis was to determine the amount of paddle shift which was caused by pressure distribution.To investigate the relationship between the package geometry and the amount of paddle shift, the present simulations considered six TQFP (Thin quad flat package) models with different geometrical parameters. The simulation results for the paddle shift were compared with the experimental results to demonstrate the accuracy of the proposed numerical approach. It was found that a good agreement exists between the two sets of results.
This paper presents, discusses, and compares results from experimental and computational studies of the plastic encapsulation process for a 144-lead TQFP package. The experimental results were obtained using an instrumented molding press, while the computational predictions were obtained using a newly-developed software for modeling transfer molding processes. Validation of the software is emphasized, and this was done mainly by comparing the computational results with the corresponding experimental measurements for pressure, temperature, and flow front advancement in the cavities and runners. The experimental and computational results were found to be in good agreement, especially for the flow-front shapes and locations.
EGA (ball grid array), one of the structures Used for semiconductor packages, involves a laminated structure. BGA inevitably involves significant warpage, owing to differences in shrinkage among constituent materials. The extent of warpage is governed by total shrinkage (= cure shrinkage + thermal shrinkage) of the epoxy molding compound that encapsulates the IC chip. In particular, the cure shrinkage exerts great influence on warpage. Cure shrinkage has been understood as the decrease in free volume at the time of curing. However, the cure shrinkage rate cannot be sufficiently explained by the free volume of the cured epoxy resin. We have developed an evaluation method based on the epoxy group reaction ratio, and have eventually confirmed that cure shrinkage depends on the reaction ratio of the epoxy group after curing, and on epoxy group density.
A TQFP (Thin Quad Flat Pack) package has been developed that has
very superior electrical and thermal performance when compared to a
plastic molded TQFP package. The high performance TQFP is based on
Olin's MQUAD technology; a packaging scheme where the plastic mold
compound is replaced by an anodized aluminum base and lid adhesively
sealed to the leadframe. The package uses the same IR or VPR board
mounting profile as a plastic package, weighs the same as a plastic
package, and is dimensionally equivalent to a plastic package
In this paper, the finite volume method (FVM) based numerical simulation is used for the flow visualization of capillary driven underfill process for different solder bump arrangements of flip chip packages is presented. Three different 3D flip chip package models are developed and simulated using computational fluid dynamic (CFD) code, FLUENT 6.3. Capillary action and cross viscosity model are taken into account in the simulation. One-line dispensing method is applied in the analysis and the volume of fluid (VOF) technique is used to track the flow front. The effect of solder balls arrangement on flow behavior and filling time is studied and the solder balls arrangement is found to affect the flow behavior and filling time. The flow patterns of simulation are observed for three flip chip packages and compared. The ability of the proposed model and FLUENT in handling flip chip underfill problems is proved to be excellent.
Interface delamination during solder reflow is a critical reliability problem for the plastic IC packages. The main objective of this study is to apply modified virtual crack closure method (MVCCM) for the analysis of interface delamination between the leadframe pad and the encapsulant during a lead-free solder reflow after the level 1 moisture preconditioning. In this study, the moisture diffusion parameters and the coefficient of moisture expansion (CME) of two different epoxy molding compounds (EMC) are characterized for moisture diffusion analysis and the deformation analysis due to hygroscopic swelling. At the same time, the entire thermal and moisture history of Thin Quad Flat Pack (TQFP) package is simulated from the start of level 1 moisture preconditioning (85 °C/85%RH for 168 h) to subsequent exposure to a lead-free solder reflow process. Finally, the transient development of the stress intensity factors due to thermal stress only Kt, hygrostress only Kh, vapor pressure only Kp and combined energy release rate Gtot are computed and studied by using MVCCM. Based on the calculated stress intensity factors and energy release rates, it seems that for the EMC, the Young’s modulus, moisture diffusion coefficient, CME and adhesion strength with leadframe at high temperature appear to be the most significant variables for the MSL performance of TQFP package and this matches well with the experimental finding.
This paper focuses on an integrated optimization problem that involves multiple qualitative and quantitative responses in the thin quad flat pack (TQFP) molding process. A fuzzy quality loss function (FQLF) is first applied to the qualitative responses, since the molding defects cannot be simply represented by the relationship between molding conditions and mathematical models. Neural network is then used to provide a nonlinear relationship between process parameters and responses. A genetic algorithm together with exponential desirability function is employed to determine the optimal parameter setting for TQFP encapsulation. The proposed method was implemented in a semiconductor assembly factory in Taiwan. The results from this study have proved the feasibility of the proposed approach.
This paper presents the simulation of pressurized underfill encapsulation process for high I/O flip chip package. 3D model of flip chip packages is built using GAMBIT and simulated using FLUENT software. Injection methods such as central point, one line, L-type and U-type are studied. Cross-viscosity model and volume of fluid (VOF) technique are applied for melt front tracking of the encapsulant. The melt front profiles and pressure field for all injection types are analyzed and presented. The pressure distribution within the flip-chip, fill volume versus filling time and viscosity versus shear rate are also plotted. The U-type injection is found to be faster in filling. The numerical results are compared with the previous experimental results and found in good conformity. The strength of CFD software in handling underfill encapsulation problems is proved to be excellent.
Several thin quad flat packages (TQFPs) are analyzed for the evaluation of G, the energy release rate based on the interfacial fracture mechanics. The purposes of this study are; (i) to obtain the values of G as a function of the length of delamination (interfacial crack) and various geometric dimensions, (ii) to obtain the values of G for the package crack, which is believed to be the subsequent stage to the full delamination, and consequently (iii) to investigate quantitatively the effect of the various geometric dimensions on the popcorn cracking during vapor-phase soldering (VPS). Also the method to compute the phase angle (or mode mixity) for the interfacial crack is presented for several TQFPs. Due to the insufficient data for Gcint, the question of whether the partial delamination for given a (delamination length or crack length) grows or not cannot be addressed. However, this can be used for the prediction of the popcorn cracking in the future study.
A lot of wedge bonding failures were observed on the leadframe (LF) type A due to non-stick on lead (NSOL) during the second wire bonding process of TQFP package. The copper ion contamination from the plating process was identified as one of the key factors that attributed to the NSOL failures. Surface analyses were performed in terms of X-ray photoelectron spectroscopy on the surface of LF type A. It was found that as received silver-plated surface of the copper LF type A was contaminated by the copper. After the copper contamination was solved in the plating process, the design of experiment was implemented for the verification of the influence of copper contamination on the quality of the second bonding process. It was confirmed that copper contamination dramatically reduced the strength of wedge bonding. The wedge pull test showed that NSOL failures were not observed after the copper ion contamination in the plating process was well controlled.
A high filler loading technique was evaluated using the simplified
packing model proposed by Ouchiyama and Tanaka (Ind. Eng. Chem. Fundam.,
vol. 23, p. 490, 1984; ibid., vol. 25, p. 125, 1986) and its effect on
the reliability of epoxy molding compound (EMC) was investigated.
Maximum packing fraction, φm, with the mixing ratio for
ternary spherical filler systems was calculated, and it was found that
the effect of macropores, which could exist in systems with more than 3
components of different filler size, should be considered in the
calculation of φm in a given filler system. Based on the
calculations, very low minimum melt viscosity of about 200 poise could
be obtained in EMC filled with 85 vol.% of silica. As the amount of
filler in EMC was increased, several properties such as coefficient of
thermal expansion, moisture absorption and strength were improved.
However, the adhesive strength to an alloy 42 leadframe decreased with
increasing filler content. Adhesive strength was more rapidly decreased
with moisture absorption. From analysis of the interface between EMC and
leadframe with X-ray photoelectron spectroscopy, the principal adhesive
mechanism was thought to be the hydrogen bond and thus the decrease in
adhesion was attributed to hydrogen bond failure due to absorbed water.
The higher adhesive strength of low level silica-filled EMC could be
explained by the low viscosity and the short intermolecular spacing with
the leadframe
Cracking of plastic packages during PCB mounting is a serious customer concern as VLSI plastic packages house ever-increasing die sizes and are made thinner. Evolutionary improvements in package materials cannot prevent package cracking in the short term, especially in thin packages. A novel design termed the `window flag' employs a central hole punched in the die pad to minimize the metal-polymer interface and maximize the silicon-mold compound interface in the die pad region. This window flag design results in crackfree performance following Level 1 preconditioning in QFPs, TQFPs and SOJs. This solution stems from the key discovery that the silicon-mold compound interface is intrinsically very strong under preconditioning stresses
The challenges presented by the low profile thin quad flat
packages (TQFPs) are the design of the mold, control of the assembly
operations of wire bonding and molding, moisture performance
characteristics, and thermal and mechanical performance. The authors
describe the design, modeling for manufacturability, and
characterization of a TQFP. The design issues of the TQFP include
package symmetry, die thickness, and wire bond loop height. Thermal,
mechanical, and electrical modeling results are presented. The assembly
process characterization and material selection are discussed. The
package performance testing includes moisture weight gain studies, moist
package cracking (popcorn) and delamination evaluation, temperature
cycle, thermal shock, and autoclave. It is apparent from the moisture
preconditioning data that care must be taken to keep the packages in a
humidity-controlled environment. A preconditioning bake of 125°C for
8 h hours should be mandatory if packages are exposed to a high humidity
environment for a long time period. However, it is clear that when
preconditioned appropriately, the TQFP package should have a reliability
performance comparable to that of a standard QFP package
In this paper, a fully three-dimensional (3-D) numerical model is developed to simulate the mold-filling behavior in the plastic encapsulation of microelectronics. The conventional Hele-Shaw approximation is inadequate to analyze such a complex process owing to the 3-D nature inherent in the molding compound flow between leadframe and mold cavity. The developed methodology combines the efficiency of SIMPLE-based finite volume method (FVM) and the robustness of VOF volume-tracking method to solve the two-phase flow field in complex mold geometry. An efficient method for automatic generation of prismatic mesh for plastic packages is also presented. The molding process of a TSOP II 54L LOC package is studied. Short-shot experiments are conducted to investigate the filling patterns at several different flow times. The close agreements between experimental data and simulated results demonstrate the applicability of the present computational model for practical plastic encapsulation simulations.
An effective and novel methodology that integrates infrared (IR) thermography measurement and a three-dimensional (3-D) finite element (FE) model is proposed for thermal characterization of packages in a steady state under a natural convection environment based on JEDEC specification . To perform surface temperature measurement using an IR thermometer, a black paint coating is applied on the surface of packages so as to calibrate the surface radiation. The associated emissivity is approximately assessed using a simple calibration experiment, and an appropriate thickness of the coating is determined. By using a typical 100-lead Thin Quad Flat package (TQFP) as the test vehicle, the proposed methodology is benchmarked by a thermal test die measurement in terms of the junction-to-ambient (J/A) thermal resistance and the chip junction temperature. To demonstrate the accuracy of the benchmarked data from the thermal test die measurement, a corresponding uncertainty analysis is performed. It is found that the worst possible uncertainty in the measured power, based on the specific power supply, is about 0.005 W and that of chip junction temperature measurement is about 0.78°C. Additional studies are performed to evaluate the feasibility of the correlation models for convective heat transfer coefficients on typical TQFP packages. It turns out that for a small device such as the TQFP package, these correlation models are fairly reliable.
Experiments were carried out using P-TQFP-176 packages to study
the mode II popcorn effect in thin packages. The doming of the package
backside was measured as a function of time and temperature. The
measurements were performed using a line projection method. An
"accelerated" increase in the doming was found to correlate with the
onset of the package crack propagation. It was shown that when a
constant critical doming angle is reached, package cracks begin to
propagate toward the surface. This critical doming angle was found to be
temperature independent between 170°C and 215°C. Furthermore the
development of the package doming with time was described by a simple
model based on the moisture diffusion from molding compound and
die-attach material in combination with a bimaterial plate theory. The
water content of the die-attach layer after preconditioning was
calculated from the model and it was found to be in good agreement with
the results of a three dimensional finite element simulation
The modified J-integral and the stress intensity factor based on
linear elastic fracture mechanics can be applied to predict the growth
of interfacial delamination in integrated circuit (IC) packages. One of
the key parameters required is the interfacial fracture toughness. This
paper describes the measurement of the interfacial fracture toughness as
a function of temperature and relative humidity using a three-point
bending test. The interfacial fracture toughness was found to decrease
with temperature and relative humidity. It is proposed that
delaminations propagate from very small voids or defects present at the
interface. The effect of the location of these interfacial defects or
cracks on delamination was studied. The IC package evaluated in this
paper was an 80-pin quad flat package with a 0.2 mm defect or crack at
the edge or at the center of the interface. It was found that as the
temperature of the package was increased, the stress intensity factor of
the edge crack was higher than that of the center crack. However,
whether the edge crack will propagate first as temperature is increased
depends on the ratio of mode II interface toughness to that of the mode
I interface toughness. For the package under investigation, it was
established that when this ratio is less than 2.69 the edge crack would
propagate first, otherwise the center crack would. For small defects, it
was found that the water vapor pressure developed at the interface did
not have a significant effect on the value of the crack-tip stress
intensity factor
Cracking of plastic packages during printed circuit board (PCB)
mounting is a serious customer concern as VLSI plastic packages house
ever-increasing die sizes and are made thinner. Evolutionary
improvements in package materials cannot prevent package cracking in the
short term, especially in thin packages. A novel design, termed the
“window flag”, employs a central hole punched in the die pad
to minimize the metal-polymer interface and maximize the silicon-mold
compound interface in the die pad region. This window flag design
results in crackfree performance following Level 1 preconditioning in
QFPs, TQFPs, and SOJs. This solution stems from the key discovery that
the silicon-mold compound interface is intrinsically very strong under
preconditioning stresses
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Thermal performance of 10 Â 10 power TQFP
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