Article

Concurrent Error Detection in Multiplexer-Based Multipliers for Normal Basis of GF(2m) Using Double Parity Prediction Scheme

Journal of Signal Processing Systems (Impact Factor: 0.6). 02/2010; 58(2):233-246. DOI: 10.1007/s11265-009-0361-4
Source: DBLP

ABSTRACT

Successful implementation of elliptic curve cryptographic systems primarily depends on the efficient and reliable arithmetic
circuits for finite fields with very large orders. Thus, the robust encryption/decryption algorithms are elegantly needed.
Multiplication would be the most important finite field arithmetic operation. It is much more complex compared to the finite
field addition. It is also frequently used in performing point operations in elliptic curve groups. The hardware implementation
of a multiplication operation may require millions of logic gates and may thus lead to erroneous outputs. To obtain reliable
cryptographic applications, a novel concurrent error detection (CED) architecture to detect erroneous outputs in multiplexer-based
normal basis (NB) multiplier over GF(2
m
) using the parity prediction scheme is proposed in this article. Although various NB multipliers, depending on aa2i = åj = 0m - 1 ti,j a2j \alpha \alpha^{{2^i }} = \sum\limits_{j = 0}^{m - 1} {t_{i,j} } \alpha^{{2^j }} , have different time and space complexities, NB multipliers will have the same structure if they use a parity prediction
function. By using the structure of the proposed CED NB multiplier, a CED scalable multiplier over composite fields with 100%
error detection rate is also presented.

Download full-text

Full-text

Available from: Chiou-Yng Lee
  • [Show abstract] [Hide abstract]
    ABSTRACT: This work develops a novel self-checking alternating logic (SCAL) bit-parallel Gaussian normal basis (GNB) multiplier with type-t over GF(2m). The proposed GNB multiplier is with both concurrent error-detection and off-line testing capabilities. The concurrent error-detection capability can give countermeasure to fault-based cryptanalysis. The off-line testing capability supports the design-for-test property. The proposed SCAL GNB multiplier can detect both permanent and transient faults. The proposed SCAL GNB is the first normal basis multiplier to have both on-line error-detection and off-line testing capabilities.
    No preview · Article · Apr 2011 · IET Information Security
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: A novel semi-systolic Gaussian normal basis multiplier with even type-t is presented. The proposed multiplier requires only about 50% space complexity of existing similar multipliers. Based on the proposed multiplier, self-checking alternating logic design of such multiplier is developed for concurrent error detection and design-for-testability. The concurrent error detection capability is elegantly needed for resistance against faultbased attacks for elliptic curve cryptosystems. The design-for-testability capability is very important for VLSI chips for manufacturability and maintainability. Our proposed selfchecking alternating logic Gaussian normal basis multiplier is the first normal basis multiplier which can provide both on-line error detection capability and off-line easily testing property.
    Full-text · Article · Oct 2011
  • [Show abstract] [Hide abstract]
    ABSTRACT: This paper proposes a low error and power optimized architecture for the multiplier based on multiplexers that aims for an optimized truncated product and power. The design of efficient truncation scheme with minimum truncation error and low power multiplier is essential for VLSI implementation of Signal Processing Devices. Various conventional array and parallel multipliers have been used and many of them boost the speed of the device at the cost of large VLSI area and high power dissipation. A novel design for multiplier based on multiplexer has been proposed in this paper considering the existing multiplexer based architecture. The proposed low error and power optimized multiplexer based truncated Multiplier was implemented in HSPICE environment in TSMC 180 nm library technology files. The results obtained are tabulated in the simulation result section, and it is observed that the proposed truncated multiplier architecture consumes approximately 35% reduction in dynamic power with minimum error. It also reduces the number of transistors by 37% when compared to the existing multiplexer based multiplier the conventional multiplexer based multiplier for 8 × 8 bit multiplication operation.
    No preview · Conference Paper · Jan 2012
Show more