0.5 V analog integrated circuits

Chapter · December 2005with5 Reads
DOI: 10.1007/1-4020-3885-2_15
In book: Analog Circuit Design, pp.329-350

Semiconductor technology scaling has enabled function density increases and cost reductions by orders of magnitudes, but for shrinking device sizes the operating voltages have to be reduced. As we move into the nanoscale semiconductor technologies, power supply voltages well below 1 V are projected. The design of MOS analog circuits operating from a power supply voltage of 0.5 V is discussed in this paper. The scaling of traditional circuit topologies is not possible anymore and new circuit topologies and biasing strategies have to developed. Several design examples are presented. The circuit implementations of gate and body-input 0.5 V operational transconductance ampli.ers and their robust biasing are discussed. These building blocks are combined for the realization of active varactor-tuned RC .lters operating from 0.5 V using standard devices with a ∣VT∣ of 0.5V in a standard 0.18 μm CMOS technology.

    • "Note that VDS.s,t is independent of the VT and practically independent of the operation region for low supply voltages. We now review the operation of basic transistor stages from a 0.5 V supply [3] since that is the lowest supply voltage foreseen in [1]. The most basic way to achieve amplification with a MOS transistor is the common source configuration with an active load1 as shown in Fig. 2 (a). "
    [Show abstract] [Hide abstract] ABSTRACT: This paper reviews the challenges and opportunities for ultra-low voltage analog integrated circuit design. The continuing scaling of CMOS technology feature sizes forces a proportional reduction of the supply voltage. The ultra-low supply voltages, down to 0.5 V, projected for the nanoscale CMOS technologies requires drastic changes in the basic circuit topologies used in analog integrated circuits. We explore the combined use of the gate and body terminal of the MOS transistor for signal input or bias control. We illustrate several true-low voltage OTA design and biasing techniques in a fully integrated 0.5 V varactor-C active filter implemented in a standard 0.18 μm CMOS technology.
    Full-text · Conference Paper · Jan 2006
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  • [Show abstract] [Hide abstract] ABSTRACT: In this dissertation a full custom Analog Front End (AFE) integrated circuit (IC) for an Electroencephalography system (EEG) is designed and implemented. The AFE consists of an ultra-low voltage amplifier and a Continuous-Time Σ∆ Analog-to-Digital converter (CT Σ∆ ADC). The AFE was implemented in 0.35 um CMOS process technology, and it works with a supply voltage of 0.5V. In order to provide a true low voltage operation, all the transistors are working in the subthreshold region. The proposed preamplifier's topology consists of an input stage based on a folded cascoded amplifier and an output stage based on a current source amplifier. The CT Σ∆ Modulator was selected to provide a very low power dissipation. The decimation stage is based in a Finite Impulse Response (FIR) filter. The Modulator works with a supply voltage of 0.5V while the FIR stage, which was not optimized, works with a 1V power supply voltage. Testing results show that the OTA has an open loop gain of 38:8dB and 18.6 dB in its 1st and 2nd stages, respectively. Also, the OTA device has bandwidths in its 1st and 2nd stages of 10.23KHz and 6.45KHz, respectively. Other obtained OTA character- istics are: output noise of 1:4mV rms@100Hz and power dissipation of 1,89uW. The ADC shows the following characteristics: SNR of 94.2dB, ENOB of 15:35bits, INL of +0.34/-2.3 LSB, DNL +.783/-.62 LSB without missing single code. The modulator dissipates only 7uW. The proposed AFE has one of the best performance among all the devices reviewed in today's literature. The AFE's performance make it suitable for biomedical low-power dissipation applications such as portable EEG devices. In addition to the CT-Σ∆ modulator developed in 0.35um CMOS technology, an alternative Modulator was designed using a 0.13um CMOS technology, based on the Discrete Time counterpart. The simulation shows a SNR of 92dB and ENOB of 14.99dB for an oversampling rate (OSR) of 150.
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