Conference Paper

A low power thyristor-based CMOS programmable delay element

Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA
DOI: 10.1109/ISCAS.2004.1328308 Conference: Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on, Volume: 1
Source: DBLP


A delay element insensitive to power supply and temperature variations becomes important as circuits speeds increase. A delay element, based on a CMOS thyristor, is proposed in this paper. This thyristor uses current rather than voltage to control the delay, exhibiting a low power supply noise, sensitivity of 94.3% and a temperature variation sensitivity of 314 PPM/°C. A technique to cancel the charge sharing effect during switching is incorporated into the delay element to further enhance power supply insensitivity. The delay element is combined with a bandgap reference voltage generator to produce a digitally controlled variable delay line. Simulation results show that the proposed delay element has lower power supply and temperature sensitivity than a classical chain of inverters. The power consumed by the proposed delay element is lower than an inverter chain, and is much lower than a differential delay element.

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Available from: E.G. Friedman
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    • "As shown in Figure 3(a), a set of regular inverters connected in a chain outputs different delayed clocks by selecting a specific output terminal [Zhang et al. 2004]. A multiplexer is employed to select a respective delay line by the binary input patterns. "
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    ABSTRACT: The feasibility of designing digitally programmable delay elements (PDEs) employing neuron-MOS mechanism is investigated in this work. By coupling the capacitors on the gate of the MOS transistor, the current flowing through the transistor can be digitally tuned without additional static power consumption. Various switching delays are generated by a clock buffer stage in this manner. Two types of neuron-MOS-based PDEs are suggested in this article. One of them is realized by directly applying capacitor-coupling technology on the transistors of an inverter as a clock buffer. The delay programmability is realized by tuning the charging/discharging current through the neuron-MOS inverter digitally. Since no additional transistor is introduced into the charging/discharging path, the performance fluctuation due to process variations on MOS transistors is reduced. The temperature effect is also partially compensated by the proposed neuron-MOS implementation. Another type of PDE circuit is proposed by employing a reliable reference-current-generator, where the neuron-MOS transistor acts as a linearly tunable resistance. A stable reference current is generated and used for charging/discharging the inverter as a clock buffer. As a result, the switching delay of the inverter is linearly programmed by digital input patterns. In general, both types of suggested PDE circuits achieve improved or fair performances over the robustness, power consumption, and linearity.
    Preview · Article · Sep 2015 · ACM Transactions on Design Automation of Electronic Systems
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    • ". Signal Q charge is generated by D NAND N enable [14]. For our application of this delay element, we needed to have the delay on the rising edge, but a " fast reset " or undelayed falling edge. Figure 3 demonstrates the desired timing of the D input and the delayed output out of the delay element. "
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    ABSTRACT: This paper presents a low-power CMOS thyristor based delay element for inclusion in standard cell ASIC libraries, and a reconfigurable delay element designed for reconfigurable devices. Our design is based on a basic delay element, which serves as a buffer which has been specially designed to have a fixed propagation delay. We present leakage power optimizations, which when applied to the circuit reduces the on-state leakage power consumption by more than 99%, while reducing the off-state leakage power by roughly 96%. We have created delay elements with delay lengths of 4, 5, 7, 9, 11, and 17 ns for inclusion in a standard cell library targeting the IBM 0.13 μm technology. The delay element is then further extended to introduce a programmability feature which allows the delay to be varied. Two reconfigurable delay elements are then added to the delay element standard cell library. The first can be configured for delays of 4, 5, or 7 ns, while the second can be programmed for delays of 9, 11, or 17 ns. Finally, potential uses of the circuits in application specific, as well as reconfigurable systems are explored.
    Full-text · Conference Paper · Jan 2009
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    • "A Thyristor-based delay element is similar to currentstarved , which uses the current mirror to adjust delay time [4]. This type of delay element adjusts the pull-up/pull-down path by altering length of the transistors in order to control the delay time. "
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    ABSTRACT: We proposed a low-power tunable delay element with several nice features. Initially, we develop this matched delay element for implementing self-timed datapath components. Surprisingly, we found this design is also suitable for many high performance applications with low power requirement after examining its circuit characteristics in more detail. Tunable and asymmetric characteristics are the two major concerns of this delay line circuit. Besides, the circuit itself also demonstrates valuable characteristics such as well adjustment to the operating temperature disparity on the delay and the technology variation-tolerant nature. In order to keep the low power intuition of utilizing asynchronous circuits, we spend a huge effort to cut down the overall power consumption. The proposed tunable delay element consumes less average power than a 4-stage minimum size inverter chain. A 4 ns and 8 ns delay implemented by our design needs only 26 muw and 30 muw respectively for the TSMC 0.35 mum technology. To the best of our knowledge, this is the lowest power consumption of the programmable delay element of the same kind so far
    Preview · Conference Paper · Dec 2006
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