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v2.2
A FORMAL HIGH LEVEL SYNTHESIS APPROACH FOR DSP ARCHITECTURES
Khaled
hl.
Elleithy and Magdy
A.
Bayoumi
The Center For Advanced Computer Studies
University of Southwestern Louisiana
Lafayette, L.4
70504,
U.S.A.
ABSTRACT
In this paper, we introduce a novel approach for high level syn
Lhesis for DSP algorithms. Two features are provided by the
approach:
completeness
and
correctness.
A
given algorithm will be
represented in a new developed language termed Algorithm
Specification Language (ASL). ASL has the abilit,y to describe any
general algorithm.
An
automatic procedure is used to transform an
ASL representation into a specific realization specification using a
correctness preserving set of transformations. The realization format
is based on representing the digital architectures by another
developed language called Realization Specification Language(RSL).
Logic Programming is used
as
a user interface for the synthesis pro
cedure.
1.
Introduction
Although Digital Signal Processing (DSP) has emerged
as
a
major technological application area, DSP design tools has not pro
gressed enough to meet the challenges of the new applications require
ments. The difficulty of developing such tools is that the chip design
involves several levels of abstraction; starting from system level
specification to the geometrical layout. The lowest level of this spec
trum is understood sufficiently well to be fairly automated, while,
developing design methods for high level synthesis is still in its
infancy stage.
Synthesising a
VLSI
architecture for a DSP algorithm starting
from a behavioral description have been reported in a number of
researches. Works reported in
[l41
depend on using only a single
fixed architecture. Works reported in
[5101
do not produce efficient
architectures
as
a result of huge underutilized communications.
Haroun and Elmasry
[11]
introduced an approach to overcome the
previous problems. Generalized Signal flow graphs (GSFG) are used
to describe the input algorithm. A number of restrictions should be
satisfied by the used GSFG.
High level synthesis approaches
for
DSP algorithms don’t only
suffer from the previous drawbacks, but also they don’t address two
focal points:
Completeness
and
Correcfness.
Reported approaches
aren’t capable of transforming a general DSP algorithm to a digital
Architecture. There are approachs to transform the class of linear
recursive algorithms to digital circuit, approaches to transform regu
Inr
itcrative algorit,hms to svqtolic
arravs.
and approaches
fc..
synthesising a specific algorithm. For the correctness aspect a form
approach is required for the synthesis process to assert the correetn,
of
the high level synthesis techniques.
In this paper, we introduce a novel approach for high level
sy~
thesis that provides two main features:
completeness
and
correctnes.5
Completeness means the ability to use the approach for any general
algorithm. Correctness is achieved by using a set of transformation.
that are proved to be correct. A formal framework for the synthesis
procedure will be developed which can be easily automated.
2.
System Overview
The proposed framework for synthesising any DSP algorithm is
shown in Figure
1.
The system is composed from two subsystems:
synthesis subsystem and userinterface subsystem.
2.1
Synthesis Subsystem
(1)
The given algorithm is specified in
a
new language, termed ASL,
which is based on precursive functions. ASL is capable of specifying
any algorithm using alimited number of constructs. Although the
constructs are very primitive, complex constructs can be used through
a developed cell library. Units that have been designed through this
design methodology can be added to the cell library.
(2)
A transformation technique is developed to transform an algo
rithm represented in ASL to a specific realization language, termed
RSL. The RSL version specifies the components and connectivity of
the digital architecture that realizes the algorithm. Every construct
in ASL has an isomorphic representation in RSL, which is the basis
of
the automated transformation. That transformation algorithm is
proved to be correct. Everything in the system
is
built from certain
primitives. The proofs of correctness are applied to these primitives.
A hierarchical proof is used for ensuring correctness at different levels.
(3)
A library of the basic functions is defined starting from the initial
functions to be used in the definition
of
larger functions. This
approach is useful for building a cell library to support the
automated synthesis system. All the basic functions that have been
designed using the proposed approach can be used
for
specifying
other functions. This technique supports a hierarchical design metho
dology in the sense that the specification can be stopped at any level
as
long as the lower levels were previously defined. When
Basic
func
tiozls
are used to represent another functions, each
Basic
function
is
written in a
M
.
2.2
User Interface Subsystem
The user interface environment that is used
for
the synthesis
process will be implemented
as
a logic programming environraent.
The logic programming environment supports specifying, simulating,
and testing Digital Signal Processing (DSP) systems. Backtracking
and
pattern matching of Prolog are employed for simulation and
.I,.I
I
~g,
respcctively. Prolog provides homogeneity to the developed
\
I
6
in
as
it
supports hierarchical development and mixing of
description at various hierarchical levels. It can be employed
for
many DSP algorithms and applications development.
Two transformation algorithms are used to link the synthesis
subsystem and the user interface subsystem. The purpose of these
two algorithms is to allow the user to use the system through the
logic programming environment without the need to know the details
of
ASL and RSL. The two algorithms are
as
follows:
897
CH28472/90/00000897
$1.00
0
1990
IEEE
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Prolog
Source
Simulation
(Design
Evaluation)
ransfor matio
Algorithm
output
Product
then the unbounded minimization
of
z
is an nargument function
.I.
I
I
defined
as
follows:
Fig.
1.
System Overview.
(1) The first algorithm is used to transform between Prolog and
ASL.
This transformation algorithm allows the user to specify his algo
rithm in terms of Prolog.
(2)
The second algorithm is used
to
transform between the RSL and
prolog. This algorithm allows
us
to have the output circuit specified
in Prolog.
3.
Algorithm Specification Language
(ASL)
Several researches have been reported for specifying the input
algorithm. Imperative languages have been used such
as:
For
tran
[
121, Pascal
[
131,
ISPS
[
14,151, and VHDL
[
161. Applicative
languages have been used such
as:
Recursion equation based
specification[l7] and Temporal Logic[l8,19].
The design specification language must be simple and semanti
cally well characterized. It must permit writing specifications using
a
few predefined objects and concepts
as
possible. Specifications must
not be prematurely committed to particular implementations.
Current hardware specification languages are far from this ideal.
The idea of representing an algorithm using a
junctional
representation
was introduced by Kleene[2O] in which any function
from numbers(strings) to numbers(strings) can be constructed using
very primitive functions and combining them in a specific manner.
Our approach for specifying an algorithm depends on using
F
recur
sive
junctions
as
a framework.
The Language consists of
Initial Functions
and
Operations.
Initial functions are very primitive functions. Three initial functions
are used:
(1)
The
zero
function which returns the value zero.
(2) The
projection
function has a
K
argument and we use it to
choose argument i.
(3) The
successor
function which increments its input by one.
Three operations are used
to
construct larger functions from smaller
functions:
(1)
(2)
(3)
(4)
(5)
(6) It is complete.
A complete description of the language syntax can be found in[2l]
Simple and semantically well characterized
It permits writing specifications using a few predefined objects
and concepts.
It is a suitable tool for formal synthesis.
It supports a hierarchical design methodology.
It supports formal verification of the initial specification.
4.
Realization Specification Language (RSL)
4.1
Realization Specification Language
The realization introduced here is described at the architectural
level. The specification describes two elements of a circuit: the com
ponents and the connectivity. The physical parameters of the circuit
are not addressed at this level of specification. The timing is not
expressed explicitly, but implicitly in terms of
registers
.
The sym
bol
p
is used to represent a register.
If
it is required to initialize the
register to a certain value
8,
then this is represented
as
PB.
(1)
If unit is a certain component that is used in the system, and inp
is any input
for
unit, then we can use this input explicitly using the
following syntax:
unit,.,
Also
an output(out)
of
unit can be used
as
follows:
unit
OY’
(2)
Identifiers starting with upper case letters are used to represent
units that will be further expressed at lower levels. Identifiers starting
with lower case letters will be used to express Basic functions.
Identifiers starting with lower case letters are used also to represent
constants, while those starting with upper case letters are used to
represent temporary variables used in computation.
(3)
Register
If it is required to use a register
Q
that is initialized to a
value
@,
then this is expressed
as
pf.
As
an Example the expression
p$suc(I)
means that
suc
unit has the register
1
connected to its input
with a value
2
as
the register initial value.
Init
statement is a
RSL
expression that can be used separately to express that register
alhpa
is
initialized to value
,9
as
follows:
Init(a,@)
Another version of Init can be used to denote the initialization of
more than one register at the same time, this is represented
as
fol
10\vs:
The previous statement means that
n
registers are initialized in
parallel such that register
a,
is initialized with the value
@,,
register
eZ
is initialized with the value
B2,
etc
...
Notice that using registers is
the only way to represent time in
our
circuits. It is assumed that all
registers are synchronized using a global clock.
In;tp(~,,B,
,
ad2
,
. . .
Q,
.Bn
i
898
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('I)
Constant
values are expressed using registers.
If
it is requir.4
to
I~nve
a constant value
(c)
in the circuit,, then this is represented
as
p
If
it is required to represent the zero function directly the following
specification is used:
Result
=
zero
zeroReadY
=
zeroConlra,
4.2
Transformation Algorithm
The transformation algorithm is based on using a onebone
mapping procedure. The algorithm takes an ASL representation and
transform each ASL's construct to an equivalent RSL representation
and an equivalent architecture implementation. The complete algo
rithm is given in(2l].
5.Implementation
of
an Innerproduct Cell
An example of an Innerproduct cell is introduced in this sec
tion. The cell has three inputs
Q,
6,
and
c,
and an output
d.
The
function of the cell is specified by:
d
=
a*b
i
c
The implementation of this equation is done in two levels. At the
first
level we need to multiply
A
and
B.
The multiplication is done
in a recursive way using repetitive addition. This can be simply
drscrihed by the following high level subroutine:
inultiplication
(n,ni)
begin
iJ
(
n
=
0)
then result
=
ni
else
begin
temp
=
iiiultiplication
((nl),ni)
result
=
addition
(
temp,
711)
end
end
The second level
of
the process is an implementation of the addition
operation. The addition is done also recursively and can be described
as
follows:
addition (n,m)
begin
q(
n
=
1)
then result
=
m
else
begin
temp
=
addition ((nl),m)
remit
=
increment (temp)
end
end
TI),.
operation of the cell can
he
described
as
follows:
innrrproduct
(a,b,c)
begin
iJ
(
c
=
0)
then result
=
multiplication
(
a,
b)
else
begin
temp
=
innerproduct
(a,b,
c1)
result
=
increment
(
temp
)
end
end
Other representations may be found for the innerproduct cell. We
are not trying to find all representations
at
this level, but we want to
mention that different representations can affect the find design. Fig
ure
2
shows the implementation of the
Innerproduct
cell, and
Appendix
I
shows the complete ASL and RSL description of this
example.
6.
Logic Programming Interface
In this section we will show how the algorithm specified in ASL
can be represented in the logic programming environment. The fol
Ready
E41"
)
P4
Fig.
2.
Iniplenientatiou
of
,ti?
Itirterproduct.
Cell
lowing steps represents the transformation algorithm:
(1)
Zero function:
is represented by the following fact:
zero
(0)
(2)
Projection function:
is represented by the following code:
pro.fect(O,l,[
I).
project(l,lX
I
YIX)
projeet(M,(X
I
Y],Result)
'
MI
is
M1,
project(M
1,
Y,Result
).
(3)
Successor function:
is
implemented
as
follows:
suc(N,M)
.
M
is
N+1
(4)
Composition
is implemented
as
follow:
z,
code
z,
code
y
code
(5)
Primitive recursion:
is expressed in the following manner:
code
for
z
code
for
y
z(Arg,,
. . .
,Arg,,O,Result)

z(Arg,,
z(Arg,,
. .
.
,Arg,,M,Result)
:
M1
is
M1
,
z(Argl,
.
' '
,Arg,,Ml,Tenip),
''
,Arg,,Result).
.v(Av,,
. .
.
,Arg,,Ml,Temp).
(6)
Unbounded minimization:
is represented in the following way:
Conclusions
In this paper
a
procedure
for
transforming general
DSP
algo
rithm to
a
digital architecture is introduced. The proposed framework
has the following advantages:
(I)
It is suitable
for
large problems since it
does
not require solving
any
NPC
problems.
(2)
The transformation algorithm is linear.
(3)
It does not require to know the target architecture in advance.
(4)
There are no restrictions imposed on the input description.
899
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The technique can be fully automated
The designer is not responsible
for
specifying the operation
sequencing
and
communications among different units.
The approach
is
applicable to any general algorithm.
Result,
=
zero
Result2
=
muzl(arg,
,
arg,
,
arg,
#
1)
Result,
=
muzdargi
,
arg2,
arq,
#
3)
Result,
=
addldResult2
~
Result,
#
add)
Initp(0,m
,
1.n)
.surronf,n,
=
tern
I

p:
snc(I)
Result

P~O(~,I,P&~I~~
#
add,,)
Ready

egP(I,m)
The addition unit code:
Result,
=
muz,(argl
#
1)
Res&
=
muzdarg,
,
arg2
,
args
#
3)
Result,

Q(Result,#suc)
I
Rule,
Initp(0,m
;
1,n)
~uc,,,~,,~
=
Resultydy
I
=
p:
suc(I)
Result

add(n,I,p&,,~tl
#
&)
Ready
=
eg?(I,m)
I
Rules+
The innerproduct cell code:
Resultl
=
muz,(arg,, arg2, arg,, arg4
#
1)
I
Rule5
Resultp
=
muzdarg,,
wg2,
arg,,
arg,
#
4)
Result,
=
temp(Result,, Result,
#
pro)
Result,
=
muzdarg,, arg2, arg,, arg,
#
4)
Results
=
addone(Result,
#
X)
Initp(0,m
,
1,n)
suc,,,,,.~
=
resultFndy
I
=
p:
suc(I)
25)
Ready
=
egP(1,m)
(26)
Result
=
innerproduct(n,I,p~,,,,,
#addone)
(27)
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900
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