A Power-Aware Technique for Functional Units in High-Performance Processors

Conference Paper · January 2006with2 Reads
DOI: 10.1109/DSD.2006.14 · Source: IEEE Xplore
Conference: Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on


    This paper presents a hardware technique to reduce the static and dynamic power consumption in functional units of a 64-bit superscalar processor. Our approach is based on substituting some of the 64-bit power-hungry adders by others with 32-bit lower power-consumption adders, and modifying the protocol in order to issue as much instructions as possible to those low power-consumption units incurring a negligible performance penalty. Our technique saves between 14.7% and a 50% of the power-consumption in the adders which is between 6.1% and a 20% of power-consumption in the execution units. This reduction is important because it can avoid the creation of a hot spot on the functional units