Architectural issues in base-station frequency synthesizers
Department of Electrical Engineering, University of Washington Seattle, Seattle, Washington, United StatesDOI: 10.1109/ISCAS.2005.1466015 Conference: Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Source: IEEE Xplore
Base station frequency synthesizers have extremely stringent specifications in terms of low integrated RMS phase error and low lock time. Satisfying both these conflicting specifications demands the selection of the right architecture. At the same time, other significant issues, such as spur suppression and tuning range, necessitate the use of allied techniques. The different architectural choices available for this application are compared vis-a`-vis their respective benefits and drawbacks. A dual-loop-PLL-based architecture that meets very strict specifications is designed and simulated at 2 GHz. This synthesizer has an integrated RMS phase error of 1° while having a phase noise of -120 dBc/Hz at 600 kHz offset. The lock time is 40 μs, and the tuning range is 100 MHz.
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ABSTRACT: A 1.5-1.6 GHz dual-loop phase-locked loop in 0.18- m CMOS locks in 40 s and draws only 26 mA from 1.8 V. The proposed techniques include a fourth-harmonic mixer that relaxes the secondary PLL requirements, and an auxiliary charge pump that speeds acquisition without affecting steady-state op- eration. The integrated RMS phase error is 1.1 and the phase noise spectral density is 116.8 dBc Hz at an offset frequency of 600 kHz. The largest in-band and reference spurs are 83 dBc and 105 dBc at frequency offsets of 500.5 kHz and 37.9 MHz, respectively.
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