Conference Paper

A low power scheduling method using dual Vdd and dual Vth

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
DOI: 10.1109/ISCAS.2005.1464680 Conference: Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on
Source: DBLP


As technology scales down to nanometer dimensions, static power consumption has become more and more important. We propose a low power method to manage power consumption; it considers dual supply voltage (Vdd) and dual threshold voltage (Vth) at the same time to deal with the scheduling problem in the behavioral synthesis stage. A flexible design space of power, and a better performance can be achieved when we use the proposed method. An algorithm combining GA (genetic algorithm) and SA (simulated annealing) is used to solve the scheduling problem. Experimental results illustrate 41.6% power reduction on average.

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    ABSTRACT: In this paper, we propose a method to solve the multiple supply voltage scheduling problem which is to assign the operational nodes of a control/data flow graph to a voltage level to minimize the average power consumption within a given computation time. Different from the previous researches focused on the operational nodes in the critical path and utilized the slack time to change the voltage of other nodes, our method can deal with all nodes without considering whether the node is in the critical path or not, and the benefit is that the voltage assignment of each node becomes more flexible. The proposed method consists of two phases, the scheduling phase and the adjusting phase, and considers both the power (delay) of the computational components and the power (delay) of the level shifters. Experimental result shows that using three voltages on a number of standard benchmarks, an average power saving of 34.23% can be obtained if the delay overhead is set as 0, and 48.07% can be obtained if the total delay is set as 1.6 times of the original delay
    No preview · Conference Paper · Jan 2006