Advanced wafer bonding solutions for TSV integration with thin wafers

Conference Paper · October 2009with9 Reads
DOI: 10.1109/3DIC.2009.5306551 · Source: IEEE Xplore
Conference: 3D System Integration, 2009. 3DIC 2009. IEEE International Conference on

    Abstract

    Due mainly to the thermal budget of CMOS devices, bonding techniques compatible with CMOS processing are limited to direct oxide bonding, metal bonding, adhesive bonding, and various hybrids of those methods. In order to facilitate thin wafer processing with existing fab equipment, we developed total solutions for temporary bonding and debonding of carrier wafers. When it comes to TSV integration, the temporary bonding process based on a spin-on adhesive is becoming the industry standard over that with a lamination tape due to better edge protection, compatibility with topographic surfaces, and better stability at higher process temperatures. The benefits with a newly developed spin-on process include temperature stability over 250degC, compatibility with bumped surfaces, short debonding time, easy thermal release, slide-off debonding, and easy cleanup with polar solvents. It is being proven that our temporary bonding and debonding techniques offer time and cost efficiency for TSV integration processes utilizing existing and established equipment and technologies. For aligned wafer-to-wafer (W2W) bonding, we developed multiple direct and indirect bond alignment methods to stack various types of substrates as well as improve alignment accuracy with minimal z-axis movement. SmartView<sup>reg</sup> alignment enables the use of any unique features on the front-side of non-IR transparent wafers for face-to-face bonding while maintaining sub-micron post-bond alignment accuracy. EVG's unique bonding processes and equipment are being widely evaluated and adopted for various TSV applications. For instance, blanket CuCu bonding performed at 415degC and 25 kN for 40 min showed neither bond interface nor voids with the quantitative post-bond adhesion energy of 10.4 J/m<sup>2</sup>. The post-bond alignment accuracy of less than 1 mum (3sigma) was also achieved with Cu patterned wafers. Chip-to-wafer (C2W) bonding, based on the thermocompression bonding mechanisms such as Cu-pol-
    ymer hybrid or Cu-Sn intermetallic compounds (IMC), is needed for future heterogeneous stacking. We developed a new advanced chip-to-wafer (AC2W) bonding concept for higher throughput and lower cost-of-ownership (CoO). The temporary pre-bonding is performed on a pick-and-place machine, followed by the permanent bonding of dies to a device wafer as a batch process in a specially designed bond chamber. A true known-good-die (KGD) stacking can be achieved through the control of the center position, the absolute value and the direction of the applied force. The average displacement with Cu-Sn-Cu bonding was 1.5 mum with the chip-to-chip deviation of 2.7 mum (3sigma).