Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM

Center for Integrated Circuits & Syst. (CICS), Nanyang Technol. Univ., Singapore, Singapore
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Impact Factor: 1.36). 03/2011; 19(2):196 - 204. DOI: 10.1109/TVLSI.2009.2033110
Source: IEEE Xplore


A new current-mode sense amplifier is presented. It extensively utilizes the cross-coupled inverters for both local and global sensing stages, hence achieving ultra low-power and ultra high-speed properties simultaneously. Its sensing delay and power consumption are almost independent of the bit- and data-line capacitances. Extensive post-layout simulations, based on an industry standard 1 V/65-nm CMOS technology, have verified that the new design outperforms other designs in comparison by at least 27% in terms of speed and 30% in terms of power consumption. Sensitivity analysis has proven that the new design offers the best reliability with the smallest standard deviation and bit-error-rate (BER). Four 32 × 32-bit SRAM macros have been used to validate the proposed design, in comparison with three other circuit topologies. The new design can operate at a maximum frequency of 1.25 GHz at 1 V supply voltage and a minimum supply voltage of 0.2 V. These attributes of the proposed circuit make it a wise choice for contemporary high-complexity systems where reliability and power consumption are of major concerns.

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    • "This paper presents a current-mode SA that improves the sensing speed and reliability of the previously published designs and at the same time reduces the power consumption. It was extensively simulated and graphically presented in comparison with other widely used SA topologies, namely the high-speed [11], decoupled latch [5], [6], the alpha latch [7] designs and read only memory system [1] designs. "
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