ArticlePDF Available

An Efficient Decoding Strategy of 2D-ECC for Optical Recording Systems

Authors:

Abstract and Figures

Two-dimensional error correction codes (2DECCs) have been the cornerstone of all three generations of optical recording - CD, DVD and BD. Research into powerful error correction methods is paramount for the development of high-capacity optical recording systems. A Reed-Solomon product-code (RS-PC) for DVD systems performs error and erasure decoding by giving and taking erasure information between two ECCs. In this paper, we will present a new error correction method that performs erasure decoding using the only erasure information supplied from a modulation code decoder - more specifically, the EFMPlus code for DVD systems. We will evaluate the decoding efficiency of the new error correction method under a channel environment with various error types.
Content may be subject to copyright.
IEEE Transactions on Consumer Electronics, Vol. 55, No. 3, AUGUST 2009
Contributed Paper
Manuscript received June 21, 2009 0098 3063/09/$20.00 © 2009 IEEE
1360
Abstract — Two-dimensional error correction codes (2D-
ECCs) have been the cornerstone of all three generations
of optical recording - CD, DVD and BD. Research into
powerful error correction methods is paramount for the
development of high-capacity optical recording systems. A
Reed-Solomon product-code (RS-PC) for DVD systems
performs error and erasure decoding by giving and taking
erasure information between two ECCs. In this paper, we
will present a new error correction method that performs
erasure decoding using the only erasure information
supplied from a modulation code decoder – more
specifically, the EFMPlus code for DVD systems. We will
evaluate the decoding efficiency of the new error correction
method under a channel environment with various error
types.
Index Terms— Erasure decoding, RS-PC, EFMPlus code
and DVD systems.
I. INTRODUCTION
Due to increasing demand for high-quality consumer
products, optical storage systems such as DVD systems
[1] and BD systems [2] have been developed to provide
higher storage capacity by leading industrial consortia.
One solution for achieving higher storage capacity is a
powerful error correction technique. In order to correct
the errors that may be included in the output stream of
a modulation code [3] decoder, optical recording
systems utilize 2-dimensional error correction codes
(2D-ECCs).
The 2D-ECCs are composed of two ECCs and
perform error and erasure decoding [4] by exchanging
erasure information between two ECCs. The 2D-ECCs
use a Reed-Solomon (RS) code [4] as an error
correction code. The reason is to increase their error
correction capability using erasure decoding of the RS
code. When the erasure decoding is employed, an RS
code with t error correction capability [4] is capable of
correcting v errors and e erasures, where 2v+e 2t. In
other words, the number of maximum correctable
errors by an RS code is t, while the number of
Jun Lee is with Digital Storage Research Laboratory, LG Electronics in
Korea (e-mail: leejun28@lge.com).
Kees A. Schouhamer Immink is with Institute for Experimental
Mathematics, Ellernstrasse 29-31, Essen, Germany (e-mail:
immink@turing-machines.com).
maximum correctable erasures by RS code is 2t. This
implies that the performance of the 2D-ECCs depend
on how efficient the used erasure decoding is.
The use of a modulation code in optical recording
systems is essential for the reduction of inter-symbol
interference, timing recovery and servo tracking. The
decoder takes the output stream of a detector as its
input. Under the decoding algorithm of the modulation
code like the slide-block algorithm [3], the decoder
decodes the output stream of a detector by searching a
look-up table. If the input of the decoder does not exist
in a look-up table, the decoder declares erasure to the
corresponding output and then assigns a pre-defined
value, which is one of the elements of a Galois field, to
the erased position. The resulting output stream
contains the errors and erasures. This erasure
information can play a significant role in improving the
error correction capability for RS decoders. However,
under the conventional erasure-decoding rule of 2D-
ECC, the 2D-ECC accomplishes the error and erasure
decoding without using this erasure information
stemming from the modulation code decoder. Also, it
is possible that the 2D-ECC exchanges the incorrect
erasure information with a high probability between
two ECCs.
This paper proposes a new error correction method
that performs error and erasure decoding using the only
erasure information supplied from the modulation code
decoder. The main goal of this paper is to increase
error correction capability by improving the erasure
decoding method of conventional 2D-ECC. This
method requires no exchange of erasure information
between two ECCs, and the erasure information only
stems from the modulation code decoder. The erasure
information may be more reliable than that of
conventional 2D-ECC because the 2D-ECC is just
designed to correct errors and erasures included in the
output stream of the modulation code decoder. The
performance of the proposed erasure decoding is
evaluated under a DVD system. Thus, the modulation
code is the EFMPlus code [5] and the 2D-ECC is a
Reed-Solomon product-code (RS-PC) [6][7].
The paper is organized as follows. In Section 2, we
overview the RS-PC for DVD system and introduce the
problems inherent in its erasure decoding methods. In
Section 3, we describe a new erasure decoding method.
In Section 4, simulated results are shown. Finally, the
conclusion is given in Section 5.
An Efficient Decoding Strategy of 2D-ECC
for Optical Recording Systems
Jun Lee and Kees A. Schouhamer Immink, Fellow, IEEE
J. Lee and K. A. Schouhamer Immink: An Efficient Decoding Strategy of 2D-ECC for Optical Recording Systems
1361
Fig. 1. RS-PC structure for DVD systems
II. RS-PC FOR DVD SYSTEMS
Erasure decoding technique plays a significant role in error
correction systems because it can correct twice as many
erasures as it can errors (e + 2v 2t). For erasure decoding,
optical recording systems adopt a 2-dimensional structure
with two ECCs. Each of the two ECCs provides erasure
information to the other. Based on that erasure information,
ECCs can perform erasure decoding in addition to error-
only decoding. Thus, the accuracy of the erasure
information supplied is a key factor in deciding the
performance of the 2D-ECCs. This Section simply
introduces the conventional error and erasure decoding
method of the RS-PC, and describes its drawbacks.
The RS-PC is illustrated in Figure 1. Each row of
information is encoded by RS (n=182, k=172, tI=5) code
(namely, inner code) over GF (28), where n and k are the
length of the codeword and information respectively. All
columns are encoded by RS (208, 192, tO=8) code (namely,
outer code).
Error and erasure decoding consists of two steps. First,
RS-PC decodes each row (column) by inner code (outer
code) and then, if the number of error bytes is over 5 (8),
such rows (columns) result either in a mis-correction or in a
decoding failure. If it is a decoding failure, the RS-PC
declares erasures to the codeword (182 bytes or 208 bytes)
in that row (column). Second, after mapping the erasure
information to error-position over outer code (inner code),
outer code (inner code) performs the error and erasure
decoding about all columns (rows).
The drawbacks of RS-PS are given as follows. In the
first decoding process, the inner code (outer code) can just
perform error-only decoding. In addition, if the number of
error bytes in each row (column) exceeds 5 (8), inner code
(outer code) declares the erasure to the codeword (182
bytes or 208 bytes) in such row (column). Note that the
symbols included in the erased row (column) may or may
Fig. 2. The incorrect erasure declaration under the conventional
decoding rule of RS-PC.
not be in error. In this case, it is possible that the inner
code(outer code) supplies the incorrect erasure information
to the outer code (inner code) and then outer code (inner
code) unreliably performs the error and erasure decoding.
Outer code also can supply inaccurate erasure information
to inner code in the same manner. If the symbol error rate
after detection is high, phenomena like the above will more
frequency happen and the decoding efficiency of the RS-
PC will decrease. In the RS-PC, the approach of iterative
error correction between inner code and outer code is
possible. However, under conventional erasure decoding
methods for RS-PC, the approach does not induce the
improvement of performance. Figure 2 shows incorrect
erasure declarations under the conventional error correction
of RS-PC. In Figure 2, vI and vO are the number of error
bytes included in the shown row and column respectively,
and eI and eO are the number of erasures declared in the
shown row and column respectively. In Figure 2, inner
code and outer code declare erasure to the shown row and
column if 2vI + eI > 10 (=2tI) and 2vO + eO > 16(=2tO),
respectively. For better decoding efficiency of error
correction systems, the research of a technique for
supplying more accurate erasure information is essential.
III. A NEW ERROR CORRCTION TECHNIQUE
The output stream of the modulation code decoder may
contain the errors and erasures, referred to as a priori
information. This output stream is rearranged for the
decoding-unit for 2D-ECC, and then it is fed to the 2D-
ECC. The RS-PC treats the a priori information as error
and performs error and erasure decoding based on the
erasure information generated by two ECCs in the error
correction process. This a priori information may be more
accurate than that of the RS-PC because the RS-PC is just
IEEE Transactions on Consumer Electronics, Vol. 55, No. 3, AUGUST 2009
1362
Fig. 3. A new error and erasure correction strategy for RS-PC
designed to control the errors and erasures contained in
the output stream of the modulation code decoder. Thus,
for erasure decoding, the consideration of this a priori
information can be expected to improve the decoding
efficiency of RS-PC. This method performs the erasure
decoding using the only a priori information without
exchanging the erasure information between two ECCs.
Under current DVD systems, this a priori
information cannot be utilized as error-position
information for RS-PC erasure decoding. The reason is
because the pre-defined value used for representing a
priori information is one of the elements over GF(28)
consisting of a codeword of error correction code. The
erasure decoding of the RS-PC using the only a priori
information can be realized by the following method.
The realization is possible by appending erasure–
indication bits to the output symbol of a modulation
code decoder. Thus, the EFMPlus code decoder outputs
9 bits, which include both the erasure-indication bit (1
bit) and its output symbol (8 bits), instead of just the 8
bits. If the erasure indication bit among the 9 bits is set
to 1, it means that the symbol at that position is erased.
A pre-defined value for expressing the a priori
information is no longer one of elements over GF (28)
and thus it is distinguished from elements consisting of
the RS codeword. For error correction, the RS-PC
searches for this pre-defined value in its decoding unit
and then maps it to the error position. Sequentially,
RS-PC can perform erasure decoding based on the only
error position. Based on this error position, repeatable
error corrections between inner code and outer code are
possible and this approach induces an incredible
performance gain compared to the same approach of
RS-PC under conventional erasure-decoding rules.
Figure 3 shows the proposed erasure decoding
procedure. In Figure 3, the modulation code is the
EFMPlus code and its decoder outputs 8 bits after
taking 16 bits as its input. Under the given decoding
rule, the decoder decodes the output stream by
searching a look-up table. If the input of the decoder
does not exist in the look-up table, the decoder outputs
9 bits of a pre-defined value. The corresponding output
is referred to as the erased symbol, or E. In case the
input of the decoder is in error but it exists in the look-
up table, the decoder outputs 9 bits in which the
erasure indication bit is set to 0. The corresponding
output is referred to as an undetected error symbol, or
U. The output stream of the decoder contains the
erased symbol E, the symbol with an error U and the
symbol without error, or C. This output stream is
rearranged to 208 by 192 bytes and is input into the
RS-PC. Finally, RS-PC accomplishes the erasure
decoding based on the only erased symbol without
exchanging erasure information between the two ECCs,
and this decoding is repeatedly performed between
inner code and outer code.
IV. SIMULATION RESULTS
In simulation, the decoding block for RS-PC is
referred to as a frame, and the number of total frames
(T) used is 200. The number of total error bytes added
to the input of the modulation code decoder is SER ×
the frame size (208 by 192 bytes), where SER (%)
stands for Symbol Error Rate. The types of errors
tested are random errors (R, %), short burst (S%), and
long burst errors (L, %). In simulation, the length of R
is 1 byte, the length of S is between 5 and 40 bytes and
the length of L is between 40 and 182 bytes. In the
channel model of this work, the ratio of E to U depends
on the types of errors tested and their distribution. All
simulation figures show the ratio of E to U and a Lena
Image reflecting the given error-types and their
distribution at specific SERs. In the figures, the X-axis
means -10log10 (SER) and the Y-axis means the
uncorrected symbol error rate. Figures 4 and 5
represent the performance of RS-PC under (R =100%)
and (R =33%, S =33% and L =34%), respectively. From
simulation results, we can identify that RS-PC using the
proposed erasure decoding (in short, I (Improved)
RSPC) outperforms conventional RS-PC irrespective of
error types and their distributions. Simulation results
reveal that the proposed erasure decoding method
clearly overcomes the drawback of conventional erasure
decoding methods, while conventional RS-PC performs
erasure decoding by exchanging incorrect erasure
information with a high probability between inner code
and outer code. In the approach of repeatable error
correction between two ECCs, the RS-PC using the
proposed erasure decoding method achieves incredible
performance gains as the number of iterations increases,
while conventional RS-PC does not. This fact implies
that two RS-PC ECCs do not generate precise erasure
information under conventional erasure decoding even if
they employ repeatable error correction.
Under the more various channel environments, we also
tested a new erasure decoding method and the results have
J. Lee and K. A. Schouhamer Immink: An Efficient Decoding Strategy of 2D-ECC for Optical Recording Systems
1363
Fig. 4. Performance comparison at R=100%
Fig. 5. Performance comparison at R=33%, S=33% and L=34%
shown that the new method outperforms the conventional
method no matter the channel environment. This section
introduces two applications exploiting the proposed criteria
applying to GS scheme with RLL constraints and the 2/3 (1,
7) PP code.
V. CONCLUSION
We have proposed an efficient erasure decoding method
using the only erasure information provided from the
modulation code decoder. This new method definitely
overcomes the drawbacks of conventional erasure decoding
methods for DVD systems. The improvement of performance
is induced by independent erasure decoding of two ECCs. The
new method achieves high performance gains irrespective of
error types and their distribution, and can easily be applied to
optical recording systems such as BD systems with minor
modifications. Thus, we conclude that the proposed method
can be a candidate for next-generation storage systems
requiring more reliable error control systems.
REFERENCES
[1] “DVD specifications for rewritable disk,” Dec. 1996.
[2] “Blu-ray disk specifications for read-only format,” Nov. 2005.
[3] K. A. S. Immink, Codes for Mass Data Storage Systems, Shannon
Foundation Publishers, 1990.
[4] S. Lin and D. J. Costello, Error control coding : Fundamentals and
application (second edition), Prentice Hall, 2004.
[5] K. A. S. Immink, “EFMPlus: the coding format of the multimedia
compact disc,” IEEE trans. on consumer electronics, vol. 41, no. 3, pp.
491-497, Aug. 1995.
[6] W. Coene, H. Pozidis and et al, “Channel coding and signal processing
for optical recording systems beyond DVD,” IEEE trans. on magnetic,
vol. 37, no. 2, pp.682~687, March 2001.
[7] H. C. Chang, C. B. Shung and C. Y Lee, “A Read-Solomon product-
code (RSPC) decoder chip for DVD applications,” IEEE Journal of
solid-state circuit, vol. 36, no. 2, pp. 229~237, Feb. 2001.
BIOGRAPHY
Jun Lee received his B.S. and M.S. degree from
Dongguk University, Seoul, Korea in 1998 and
2000, respectively. Since March 2000, he has
been a Ph.D. student in Dept. of Electronic
Engineering at Dongguk University. In 2003, he
received Ph. D. degree and he joined the faculty
of Samsung Advanced Institute of Technology
(SAIT), Suwon, Korea, and he is currently
working with LG Electronics. His research
interests are signal processing and coding for
storage systems and communication theory.
Kees Schouhamer Immink received his PhD
degree from the Eindhoven University of
Technology. He was with Philips Research
Labs in Eindhoven from 1968 till 1998. He
founded and became president of Turing
Machines Inc. in 1998. He is, since 1994, an
adjunct professor at the Institute for
Experimental Mathematics, Essen University,
Germany. Immink designed coding techniques
of virtually all consumer-type digital audio and
video recording products, such as Compact Disc, CD-ROM, CD-Video,
Digital Audio Tape recorder, Digital Compact Cassette system, DCC,
Digital Versatile Disc, DVD, Video Disc Recorder, and Blu-ray Disc. He
received widespread recognition for his many contributions to the
technologies of video, audio, and data recording. He received a
Knighthood in 2000, a personal ‘Emmy’ award in 2004, the 1996 IEEE
Masaru Ibuka Consumer Electronics Award, the 1998 IEEE Edison Medal,
1999 AES Gold Medal, and the 2004 SMPTE Progress Medal. He was
named a fellow of the IEEE, AES, and SMPTE, and was inducted into the
Consumer Electronics Hall of Fame, and elected into the Royal
Netherlands Academy of Sciences and the US National Academy of
Engineering. He served the profession as President of the Audio
Engineering Society inc., New York, in 2003.
... The ECC used in this work for meaningless reversible degradation is a systematic Berlekamp Reed-Solomon [13]. This ECC algorithm is very popular, being frequently used in 2D-Barcodes, satellite communications, and optical recording systems, like CD, DVD, and Bluy-Ray [14], [15], [16]. ...
... The RS codes can correct t burst symbol errors, i.e., tw burst bit errors. Moreover, by using erasure decoding, RS codes can correct 2tw burst errors [41]. The erasure decoding requires other error control codes to provide erasure information. ...
Article
Full-text available
This paper investigates the decoding performance of channel-coded ship-based satellite communications on-themove (SSCOTM) between ships and satellites. In practical communications, ship antennas deviated from satellites by wind waves suffer rapid channel degradation with serious burst errors and even losing all the data. To address this issue, we first establish a mathematical model to study the influence of wind waves and derive the effective signal-to-noise ratio (SNR) in SSCOTM. Second, we propose a vertical Reed Solomon (RS) with Cyclic Redundancy Check (CRC) and Low Density Parity Check (VRC-LDPC) code where the RS code and LDPC code are treated as the inner code and outer code to correct both burst and random errors, respectively. Moreover, both the encoder and the decoder of the proposed VRC-LDPC can be carried out in parallel implementations. Finally, simulation results show that the proposed VRC-LDPC performs much better than the conventional codes of Consultative Committee for Space Data Systems (CCSDS) standard. Thus, this paper provides an excellent alternative channel code for reliable error-correction systems of SSCOTM.
... Additionally, HD2DC can have one of these 3 error correction levels: Low (10%), Medium (20%), and High (30%). The proposed HD2DC barcode uses a type of Reed-Solomon error-correction algorithm [19] known as systematic Berlekamp-Massey algorithm [4]. This algorithm uses non-binary Bose, Chaudhuri, and Hocquenghem (BCH) codes, which guarantee a maximum separation distance and a high burst error-correction capability [4]. ...
Article
Full-text available
Two-dimensional barcodes have been a topic of research for several decades. Recently, new requirements have been imposed on 2D-barcode applications, which include the capability of storing information into a small printed area. This particular requirement is specially important for applications that store cryptographic data, which needs be processed off-line. This is the case of barcodes in products like cigarettes and medicines, which store data used for validation and product verification. In this paper, we propose a 2D-colored barcode: The High Density Two-Dimensional Code (HD2DC), which is currently one of the 2D-barcodes with the highest data density. HD2DC can be generated in 8 different sizes, with 5 or 8 channel colors. To increase robustness, the system uses a Reed-Solomon error correction algorithm with 3 different levels, providing between 10% and 30% of error correction capability. We tested the HD2DC simulating two scenarios: a print-scan channel and a lossy compression stage. Results show that the proposed color barcode, besides being able to store a high density of data, is very robust to channel and compression degradations. © 2018 Springer Science+Business Media, LLC, part of Springer Nature
... Un ejemplo de éste, puede ser un arreglo compuesto por un codificador horizontal RS H (255,239) para el procesamiento de las filas y un codificador vertical RS V (255,247) para el procesamiento de las columnas [26], donde la codificación realimentada depende de los resultados de los símbolos de redundancia generados por la primera codificación, como se muestra en la Figura 4. A partir de estos esquemas o arreglos de códigos concatenado se estudia un esquema mixto, en el cual se pueda seleccionar la configuración de forma selectiva, la concatenación paralela o concatenación serial, con procesamiento paralelo de los datos D(x), por ambos codificadores RS y una realimentación de los símbolos de redundancia selectiva, la cual se puede habilitar al codificador correspondiente, manejada a través de habilitadores, partiendo de una generalización del modelo, por medio de la concatenación de las salidas de los codificadores RS, esto implementado de forma matricial, como se muestra en la Figura 5. ...
Article
Full-text available
In this research, a logical-mathematical model of the Reed Solomon encoder is developed in two-dimensions, based on the optimized model of the LFSR components (linear feedback shift registers) and RS coders, considering the fractal structure of these circuits and their extrapolation to code concatenation schemes. This is for the purpose of generating the hardware descriptor code in VHDL, applying concepts of iterated functions. The methods considered correspond to the mathematical interpretation of the circuits and identification of correspondence between the equations that describe the mathematical behavior of these elements. In this way, we obtain as a result the model of equations of the constitutive circuits of the 2D-RS, recognizing a highly efficient solution, due to the optimization of circuit stages. This model is a contribution in the design of complex encoders with free hardware, since it simplifies the VHDL description of the encoder and promotes its updating over time. Resumen En esta investigación se desarrolla un modelo lógico-matemático del codificador Reed Solomon en dos dimensiones, basada en el modelo optimizado de los componentes LFSR (registros desplazamientos con realimentación lineal) y codificadores RS, considerando la estructura fractal de estos circuitos, y su extrapolación a los esquemas de concatenación de códigos. Esto con el propósito de generar el código descriptor de hardware en VHDL, aplicando conceptos de funciones iteradas. Los métodos considerados corresponden a la interpretación matemática de los circuitos e identificación de correspondencia entre las ecuaciones que describen el comportamiento matemático de estos elementos. De esta manera, se obtiene como resultado el modelo de ecuaciones de los circuitos constitutivos del 2D-RS, reconociendo una solución altamente eficiente, debido a la optimización de etapas del circuito. Este modelo constituye un aporte en el diseño de codificadores complejos con hardware libre, ya que simplifica la descripción VHDL del codificador y promueve su actualización en el tiempo. Palabras Claves: Modelo lógico-matemático, Diseño Hardware Libre, Códigos 2D-RS Reconfigurable, Reed Solomon, VHDL, FPGA.
... Un ejemplo deéste, puede ser un arreglo compuesto por un codificador horizontal RS H (255, 239) para el procesamiento de las filas y un codificador vertical RS V (255, 247) para el procesamiento de las columnas [24], donde la codificación realimentada depende de los resultados de los símbolos de redundancia generados por la primera codificación, como se muestra en la A partir de estos esquemas o arreglos de códigos concatenado se estudia un esquema mixto, en el cual se pueda seleccionar la configuración de forma selectiva, la concatenación paralela o concatenación serial, con procesamiento paralelo de los datos D(x), por ambos codificadores RS y una realimentación de los símbolos de redundancia selectiva, la cual se puede habilitar al codificador correspondiente, manejada a través de habilitadores, partiendo de una generalización del modelo, por medio de la concatenación de las salidas de los codificadores RS, esto implementado de forma matricial, como se muestra en la Figura 5. Es de hacer notar, que para el caso del codificador concatenado paralelo se puede sustituir el multiplexor de salida, por un elemento lógico que permita la concatenación matricial de la salida de cada codificador RS componente, expresado como ...
Article
Full-text available
En esta investigación se desarrolla un modelo lógico-matemático del codificador Reed Solomon en dos dimensiones, basada en el modelo optimizado de los componentes LFSR (registros desplazamientos con realimentación lineal) y codificadores RS, considerando la estructura fractal de estos circuitos, y su extrapolación a los esquemas de concatenación de códigos. Esto con el propósito de generar el código descriptor de hardware en VHDL, aplicando conceptos de funciones iteradas. Los métodos considerados corresponden a la interpretación matemática de los circuitos e identificación de correspondencia entre las ecuaciones que describen el comportamiento matemático de estos elementos. De esta manera, se obtiene como resultado el modelo de ecuaciones de los circuitos constitutivos del 2D-RS, reconociendo una solución altamente eficiente, debido a la optimización de etapas del circuito. Este modelo constituye un aporte en el diseño de codificadores complejos con hardware libre, ya que simplifica la descripción VHDL del codificador y promueve su actualización en el tiempo.
... CQR Code-5 uses the Reed-Solomon error-correction algorithm to protect the transmitted information [10]. This errorcorrection algorithm is very popular, being frequently used in satellite communications and optical recording systems, like CD, DVD and Bluy-Ray [11]. The Reed-Solomon algorithm takes as input k symbols of s bits and adds n − k redundancy symbols, forming a code-word of n symbols. ...
Conference Paper
Full-text available
This paper presents an implementation of a colored 2D-barcode which is based on the structure of the CQR Code (Colored Quick Response Code). While the first version of the CQR Code (CQR Code-5) is a 2-D barcode of 5 colors, this new version (CQR Code-9) has 9 colors. In this paper we describe the implementation details of this new CQR Code. This new version of the CQR Code can store up to 2,048 information bits, requiring 4,576 redundancy bits. The Reed-Solomon error correction algorithm provides an error correction rate of 34.54%. Experimental tests were performed by printing CQR Codes in a 1.3 cm × 1.3 cm area. Results show that the CQR Code-9 is suitable for cryptographic applications that require that a high number of bits be stored in a small printed area.
... In these cases, the product and concatenation codes require RS codes to provide reliable error-detection or erasure information. In particular, the RSPC and Picket codes employ erasures-and-errors decoding which requires that some RS codes should supply accurate erasure information to others [17][18]. It should be noted that the erasures-anderrors decoding plays an important role in RS codes [19]. ...
Article
In storage and communication systems, the product and concatenation codes, which consist of Reed–Solomon (RS) codes and other error-correction codes, can be utilized to effectively correct burst errors by performing erasures-and-errors decoding. However, the RS codes have two drawbacks: 1) the RS decoders may not detect received erroneous codewords, and 2) the RS decoders may generate valid codewords which are not equal to the transmitted codewords. In the implementation of the product and concatenation codes, such decoding drawbacks can cause the RS code to provide incorrect error-detection information or erasure information to other error-correction codes, resulting in unreliable error-correction performance of the systems. In this study, we propose a new product code to overcome these drawbacks by studying the RS product code (RSPC). The new code combines CRC code with RSPC which is called as CRSPC. In addition, the results of experiments show that the new CRSPC can significantly reduce the probabilities of these drawbacks, thereby improving the performance of erasures-and-errors decoding. With minor modifications, the CRSPC algorithm can be applied to Blue-ray disc systems which have powerful recording functions in multimedia.
Conference Paper
This paper presents an implementation of a colored 2D-barcode which is based on the structure of the CQR Code (Colored Quick Response Code). While the first version of the CQR Code (CQR Code-5) is a 2-D barcode of 5 colors, this new version (CQR Code-9) has 9 colors. In this paper we describe the implementation details of this new CQR Code. This new version of the CQR Code can store up to 2,048 information bits, requiring 4,576 redundancy bits. The Reed-Solomon error correction algorithm provides an error correction rate of 34.54%. Experimental tests were performed by printing CQR Codes in a 1.3 cm × 1.3 cm area. Results show that the CQR Code-9 is suitable for cryptographic applications that require that a high number of bits be stored in a small printed area.
Article
Reed-Solomon product-code (RSPC), which performs erasures-and-errors decoding utilizing inner and outer Reed-Solomon (RS) codes, can be used to effectively correct burst errors in DVD systems. RSPC has the advantages of high error correction capabilities and high code rate. In this study, we present that the maximum correctable burst length of RSPC in DVD systems is 2917 bytes. However, by applying iterative decoding, the RSPC can obtain the length, resulting in the increase of execution time and energy consumption. In order to combat these unnecessary operations, we present a new encoding and decoding scheme. Experimental results show that the new scheme can significantly decrease the probability of decoding errors, thereby improving the error correction performance of DVD systems.
Article
This paper presents an improved data hiding technique based on BCH (n,k,t ) coding. The proposed embedder hides data into a block of input data by modifying some coefficients in the block in order to null the syndrome. The proposed embedder can hide data with less computational time and less storage capacity compared to the existing methods. The complexity of the proposed method is linear while that of other methods are exponential for any block size n. Thus, it is easy to extend this method to a large n. The BCH syndrome coding for steganography is now viable ascribed to the reduced complexity and its simplicity of the proposed embedder.
Book
Full-text available
Preface to the Second Edition About five years after the publication of the first edition, it was felt that an update of this text would be inescapable as so many relevant publications, including patents and survey papers, have been published. The author's principal aim in writing the second edition is to add the newly published coding methods, and discuss them in the context of the prior art. As a result about 150 new references, including many patents and patent applications, most of them younger than five years old, have been added to the former list of references. Fortunately, the US Patent Office now follows the European Patent Office in publishing a patent application after eighteen months of its first application, and this policy clearly adds to the rapid access to this important part of the technical literature. I am grateful to many readers who have helped me to correct (clerical) errors in the first edition and also to those who brought new and exciting material to my attention. I have tried to correct every error that I found or was brought to my attention by attentive readers, and seriously tried to avoid introducing new errors in the Second Edition. China is becoming a major player in the art of constructing, designing, and basic research of electronic storage systems. A Chinese translation of the first edition has been published early 2004. The author is indebted to prof. Xu, Tsinghua University, Beijing, for taking the initiative for this Chinese version, and also to Mr. Zhijun Lei, Tsinghua University, for undertaking the arduous task of translating this book from English to Chinese. Clearly, this translation makes it possible that a billion more people will now have access to it. Kees A. Schouhamer Immink Rotterdam, November 2004
Article
Full-text available
We report on an alternative to Eight-to-Fourteen Modulation (EFM), called EFMPlus, which has been adopted as coding format of the MultiMedia Compact Disc proposal. The rate of the new code is 8/16, which means that a 6-7% higher information density can be obtained. EFMPlus is the spitting image of EFM (same minimum and maximum runlength, clock content etc). Computer simulations have shown that the low-frequency content of the new code is only slightly larger than its conventional EFM counterpart.
Article
High-capacity optical recording beyond DVD is physically made possible by using blue lasers with shorter wavelengths, and improved lenses with high numerical aperture. In collaboration with Sony, a new optical disc format for a real-time Digital Video Recording system (DVR) has been developed. Signal processing plays a key role in the optimization of disc capacity together with system margins of the optical drive. For the new format, new modulation codes have been designed for the rewritable version (parity-preserving code) and the read-only version (combi-code). For bit-detection in the rewritable format, a nonrecursive algorithm with PRML-like performance is devised. Finally, a new ECC code, called the picket code, was designed in order to cope with multiple long burst errors, on top of the usual random errors of the channel
Article
In this paper, a Reed-Solomon Product-Code (RS-PC) decoder for DVD applications is presented. It mainly contains two frame-buffer controllers, a (182, 172) row RS decoder, and a (208, 192) column RS decoder. The RS decoder features an area-efficient key equation solver using a novel modified decomposed inversionless Berlekamp-Massey algorithm. The proposed RS-PC decoder solution was implemented using 0.6 μm CMOS single-poly double-metal (SPDM) standard cells. The chip size is 4.22×3.64 mm<sup>2</sup> with a core area of 2.90×2.88 mm <sup>m</sup>m<sup>2</sup>, where the total gate count is about 26 K. Test results show that the proposed RS-PC decoder chip can support 4×DVD speed with off-chip frame buffers or 8×DVD speed with embedded frame buffers operating at 3 V
A Read-Solomon product-code (RSPC) decoder chip for DVD applications He received widespread recognition for his many contributions to the technologies of video, audio, and data recording
  • H C Chang
  • C B Shung
  • C Lee
H. C. Chang, C. B. Shung and C. Y Lee, " A Read-Solomon product-code (RSPC) decoder chip for DVD applications, " IEEE Journal of Digital Audio Tape recorder, Digital Compact Cassette system, DCC, Digital Versatile Disc, DVD, Video Disc Recorder, and Blu-ray Disc. He received widespread recognition for his many contributions to the technologies of video, audio, and data recording. He received a Knighthood in 2000, a personal 'Emmy' award in 2004, the 1996 IEEE Masaru Ibuka Consumer Electronics Award, the 1998 IEEE Edison Medal, 1999 AES Gold Medal, and the 2004 SMPTE Progress Medal. He was named a fellow of the IEEE, AES, and SMPTE, and was inducted into the Consumer Electronics Hall of Fame, and elected into the Royal Netherlands Academy of Sciences and the US National Academy of Engineering. He served the profession as President of the Audio Engineering Society inc., New York, in 2003.