High velocity Si-nanodot : A candidate for SRAM applications at 16nm node and below
STMicroelectronics, Crolles, FranceConference: VLSI Technology, 2009 Symposium on
Source: IEEE Xplore
We report a new nanodot MOSFET, based on the use of Bulk wafer and Silicon-On-Nothing technology, requiring neither CMP nor extra photo-lithographic step. SRAM-application oriented nanodot devices were fabricated using this new process. Record performance among the nanometric gate-all-around MOSFET state-of-the-art is obtained thanks to a high quality transport.
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ABSTRACT: This work presents an experimental study in order to evaluate the quality of transport in the most advanced state-of-the-art gate-all-around devices in term of performances. Experiments have been done on silicon channel devices with metal/high-k gate all-round stack at aggressive dimensions (L × W × TSi = 25nm × 20 nm × 10nm). We deeply investigated the mobility and the limiting velocity in order to evaluate the possible occurrence of ballisticity. Interest of the gate-all-around in terms of effective current and parasitic capacitance has then been studied in the scope of elementary circuit perspectives.
Conference Paper: Si nanowire device and its modeling[Show abstract] [Hide abstract]
ABSTRACT: Because of its nature of effectively suppressing the off-leakage current with gate around configuration, the Si nanowire FET has been thought be the ultimate structure for for ultra-small CMOS devices towards their downsizing limit. Recently, several experimental data of Si nanowire FETs with very high on-current much larger than that of planar MOSFETs have been published. Thus, Si nanowire FETs are now drawing attention as the most promising candidate for the mainstream CMOS devices in 2020s. In order for the Si nanowire FETs to be introduced into integrated circuits, good compact models which circuit designers can easily handle with are essential. However, it is a really challenging task to establish the compact model, because I<sub>d</sub>-V<sub>d</sub> characteristics of the Si nanowire FETs are affected by the band structure of the nanowire, and the band structure are very sensitive with the nanowire diameter, cross-sectional shape, crystal orientation, mechanical stress, and interface states. In this paper, recent research status of Si nanowire FETs in experimental and theoretical works are described.
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ABSTRACT: Gate semi-around silicon nanowire (SiNW) FETs have been fabricated and their electrical characteristics, especially on the drivability, have been assessed for future high performance devices. Among different wire size, a SiNW FET with a cross-section of 12 × 19 nm<sup>2</sup> has shown an improvement in the on-current (I<sub>ON</sub>) when normalized by the channel peripheral length. A high I<sub>ON</sub> over 1600 μA/μm at an overdrive voltage of 1 V has been achieved with a gate length and an oxide thickness of 65 and 3 nm, respectively. The origin of the high drivability has been speculated by higher carrier density, improved carrier mobility and the reduction in the series resistance.
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