Polarity dependent breakdown of the high-κ/SiOx gate stack: A phenomenological explanation by scanning tunneling microscopy

Applied Physics Letters (Impact Factor: 3.3). 06/2008; 92(19):192904 - 192904-3. DOI: 10.1063/1.2926655
Source: IEEE Xplore


From scanning tunneling microscopy, we present unambiguous evidence of thermally induced localized conduction paths exhibiting an asymmetrical conduction property in the high- κ gate stack. The tunneling current under gate injection biasing is found to be much larger than that under substrate injection biasing after a 700 ° C postdeposition anneal, i.e., the localized paths exhibit a much lower resistance under gate injection biasing. This finding provides a phenomenological explanation for the polarity dependent breakdown of the high- κ gate stack as observed from electrical stressing of large-area metal-oxide-semiconductor capacitors.

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    ABSTRACT: Reliability study of high-κ (HK) gate dielectric based transistors has become imperative for the current and future CMOS technology nodes as the industry shifts towards replacement of conventional silicon oxynitride (SiON) with hafnium-based oxides. One of the key requirements of any oxide reliability study is a quantitative assessment of the time dependent dielectric breakdown (TDDB) lifetime using suitable statistical models. Direct extension of the simple statistical model used for SiON to the HK is complicated by the presence of the interfacial sub-oxide layer (IL, SiO<sub>x</sub>) which is sandwiched between the HK and Si substrate. Given the dual-layer HK-IL dielectric stack, it is necessary to develop new statistical models and electrical test algorithms that can enable us to decode the reliability and Weibull slope of the individual HK and IL layers so that the relative reliability of these two layers can be studied to identify the layer which serves as a “savior” in prolonging the front end reliability of current HK based logic devices. In this study, we propose a new cumulative damage statistical model in conjunction with a two step voltage stress electrical test algorithm for sequential HK-IL breakdown which enables us to analyze the TDDB reliability of HK and IL separately.
    Full-text · Conference Paper · Jun 2010
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    ABSTRACT: In order to achieve aggressive scaling of the equivalent oxide thickness (EOT) and simultaneously reduce leakage currents in logic devices, silicon-based oxides (SiON / SiO<sub>2</sub>) have been replaced by physically thicker high-κ transition metal oxide thin films by many manufacturers starting from the 45 nm technology node. CMOS process compatibility, integration and reliability are the key issues to address while introducing high-κ at the front end. In this study, we analyze in-depth the reliability aspect of high-κ dielectrics focusing on both the time-dependent-dielectric breakdown (TDDB) and the post breakdown evolution stage. Electrical characterization, physical failure analysis, statistical reliability modeling as well as atomistic simulations have all been used to achieve a comprehensive understanding of the physics of failure in HK and the associated microstructural defects and failure mechanisms. The role played by different gate materials ranging from poly-Si → FUSI → metal gate and different HK materials (HfO<sub>2</sub>, HfSiON, HfZrO<sub>4</sub>) is also investigated. Based on the results obtained, we emphasize the need and propose a few approaches of design for reliability (DFR) in high-κ gate stacks.
    No preview · Conference Paper · Jun 2010
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    ABSTRACT: Conductive atomic force microscopy (C–AFM) in ultra high vacuum (UHV) has been used to characterize charge trapping in ultrathin as–deposited oxide films of 2–4 nm (HfO2)x(SiO2)1-x/SiO2 multilayer gate stacks. Pre– and post–stress/breakdown (BD) dielectric degradation is analyzed on a nanoscale. A systematic observation probes stress induced trap generation facilitating physical stack BD. Degradation is considered in terms of the pronounced localized leakage contribution through the high–κ and interlayer SiOx. Simultaneous nanoscale current–voltage (I-V) characteristics and C–AFM imaging illlutrates charge trapping/decay from the native or stress induced traps with intrinsic charge lateral propagation. A post–stress/BD constant voltage imaging shows effects of stress bias polarity on the BD induced topography and trap assisted nano–current variations. Physical attributes of deformed artifacts relate strongly to the polarity of electron injection (gate or substrate) so discriminating the trap generation in high–κ and interlayer SiOx revealing non–homogeneous (dynamic) nature of leakage.
    No preview · Article · Jan 2011 · MRS Online Proceeding Library
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