Article

Novel co-design of NAND flash memory and NAND flash controller circuits sub-30nm low-power high-speed Solid-State Drives (SSD)

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Abstract

As the cell size of the NAND flash memory has been scaled down by 40%-50% per year and the memory capacity has been doubling every year, a solid-state drive (SSD) that uses NAND as mass storage for personal computers and enterprise servers is attracting much attention. To realize a low-power high-speed SSD, the co-design of NAND flash memory and NAND controller circuits is essential. In this paper, three new circuit technologies, the selective bit-line precharge scheme, the advanced source-line program, and the intelligent interleaving, are proposed. In the selective bit-line precharge scheme, an unnecessary bit-line precharge is removed during the verify-read and consequently the current consumption decreases by 23%. In the advanced source-line program scheme, a hierarchical source-line structure is adopted. The load capacitance during the program pulse is reduced by 90% without a die size overhead. As a result, the current consumption is reduced by 48%. Finally, with the intelligent interleaving, a current peak is suppressed and a high-speed parallel write operation of the NAND flash memories is achieved. By using these three technologies, both the NAND flash memory and the NAND controller circuits are best optimized. At the sub-30 nm generation, the current consumption of the NAND flash memory decreases by 60% and the SSD speed improves by 150% without a cost penalty or circuit noise.

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... With the aggressive scaling down of the minimum feature size of memory bit cells, the capacity of NAND flash memory is drastically increasing, expediting NAND flash memory bit growth. Despite this merit, bit-line (BL) capacitances, which are shared by memory bit cells, are increasing abruptly [1] since the height of BLs is not reduced to maintain low resistances. ...
... Performance_NAND is the write speed of a single NAND flash memory chip. In the SSD operation, since peak ICC increases as N increases, the maximum N is restricted by an ICC constraint [1]. One of the most well-known strategies for improving Performance_NAND is to use a cache program operation [7]. ...
... In NAND flash memories, various techniques for reducing peak ICC have been proposed [1]- [6]. In [1], a selective BL pre-charge, source-line program, and an intelligent interleaving scheme are proposed. In this work, a selective BL pre-charge scheme eliminates unnecessary BL precharging and the intelligent interleaving scheme avoids peak ICC through a power detector in the multi-wave interleaving operation. ...
Article
In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory - namely, a program Cache Busy lime (tPCBSY control method The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit-line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number; cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid-state drive.
... The NAND flash memory is becoming one of the most widely used nonvolatile memories because of its fast random access performance, shock resistance, and low power consumption [1,2]. The NAND flash memory stores data as the threshold voltage of each flash cell, and each cell consists of a floating-gate transistor. ...
... The NAND flash memory is continuously scaled down to achieve high storage capacities and low costs [3]. This phenomenon is a result of two key trends: (1) effective process technology scaling; (2) multilevel (e.g., MLC, TLC) cell data coding. However, the rapid increase in storage density of the NAND flash also makes its reliability continue to decrease [4][5][6][7]. ...
... Energy consumption is an important factor among commercial and enterprise SSDs. These days, SSD's energy consumption has increased due to the increased capacitance of the flash memory bit lines in the downscaled SSD architectures [6]. The energy consumption criterion has long been studied in many other fields and literature. ...
... Here, the threshold voltage of each cell is affected by the change in the threshold voltage of its adjacent cells. Reference [ In Equation 6, and indicate the ℎ bitline and the ℎ wordline in a SSD block. ...
Preprint
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In this work, we propose a novel coding scheme which based on the characteristics of NAND flash cells, generates codewords that reduce the energy consumption and improve the reliability of solid-state drives. This novel coding scheme, namely Inverted Limited Weight Coding (ILWC), favors a greater number of '1's appearing in its generated codewords at the cost of added information redundancy, as a form of flag bits. This increase in the number of bits valued as logical '1', in the generated codewords, will increase the number of cells that have lower threshold voltages. Through cells with lower threshold voltages, ILWC fruitfully reduces the SSD's program operation energy consumption. Moreover, it increases the SSD's data retention rate and reliability by decreasing the threshold voltage of the cells. The evaluation of our proposed coding method on three different SSDs, indicates more than 20% reduction in the SSD's program operation energy consumption. In addition, ILWC improves the cells' data retention rate by decreasing their intrinsic electric field by more than 18%. Moreover, the SSD's cell-to-cell coupling noise is diminished with the help of 35% reduction in the worst-case threshold voltage shift in a cell's adjacent cells. All this leads to 5.3% reduction in the MLC's cell error rate. In addition, ILWC achieves 37.5% improvement in the performance of the SSD program operation.
... Energy consumption is an important factor among commercial and enterprise SSDs. These days, SSD's energy consumption has increased due to the increased capacitance of the flash memory bit lines in the downscaled SSD architectures [6]. The energy consumption criterion has long been studied in many other fields and literature. ...
... Here, the threshold voltage of each cell is affected by the change in the threshold voltage of its adjacent cells. Reference [ In Equation 6, and indicate the ℎ bitline and the ℎ wordline in a SSD block. ...
Preprint
Full-text available
In this work, we propose a novel coding scheme which based on the characteristics of NAND flash cells, generates codewords that reduce the energy consumption and improve the reliability of solid-state drives. This novel coding scheme, namely Inverted Limited Weight Coding (ILWC), favors a greater number of '1's appearing in its generated codewords at the cost of added information redundancy, as a form of flag bits. This increase in the number of bits valued as logical '1', in the generated codewords, will increase the number of cells that have lower threshold voltages. Through cells with lower threshold voltages, ILWC fruitfully reduces the SSD's program operation energy consumption. Moreover, it increases the SSD's data retention rate and reliability by decreasing the threshold voltage of the cells. The evaluation of our proposed coding method on three different SSDs, indicates more than 20% reduction in the SSD's program operation energy consumption. In addition, ILWC improves the cells' data retention rate by decreasing their intrinsic electric field by more than 18%. Moreover, the SSD's cell-to-cell coupling noise is diminished with the help of 35% reduction in the worst-case threshold voltage shift in a cell's adjacent cells. All this leads to 5.3% reduction in the MLC's cell error rate. In addition, ILWC achieves 37.5% improvement in the performance of the SSD program operation.
... However, SSDs can only erase data in the unit of block. Therefore, in the case of overwriting data, SSDs need to perform out-of-place update [27]. When overwrite operations are executed, a flash translation layer (FTL) of SSD writes new data in free pages in other blocks and invalidates original data. ...
Article
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Recently, flash-based solid-state drives (SSDs) are widely used in industry and academia due to their higher bandwidth and lower latency compared with traditional hard disk drives (HDDs). Furthermore, SSDs with the Non-Volatile Memory Express (NVMe) interface can provide higher performance and ultra-low latency compared with the Serial AT Attachment (SATA) SSDs. Due to their high performance, NVMe SSDs are adopted in many systems as fast storage devices. However, the performance of NVMe SSDs can be negatively affected by I/O access patterns. For example, random write access patterns can have negative impacts on the performance due to the unique characteristics of SSDs such as out-of-place update and garbage collection. In this paper, we propose an address remapping scheme to improve the I/O performance of NVMe SSDs. Our proposed scheme transforms random access patterns into sequential access patterns in the NVMe device driver. This allows our scheme to improve the I/O performance of NVMe SSDs while supporting widely used file systems such as EXT4, XFS, BTRFS, and F2FS without any modification to the device. Experimental results show that our proposed scheme can improve the performance of NVMe SSD by up to 64.1% compared with the existing scheme.
... In building such an epidermal electronic system with information storage capability, a key bottleneck lies in the lack of flexible nonvolatile memory that has specifications comparable to those of commercial devices. Nonvolatile memories, especially the dominant type, flash memories, that can retain stored information for later retrieval and analysis, are expected to have low program and erase voltages of less than 10 V for low power consumption, a long retention time of over 10 8 s for good information storage stability, and a good endurance for robust cyclic operation of over 10 5 cycles in commercial use (17,18). Because of the limited yield and insufficient uniformity of flexible memory devices, which are mainly constrained by the limited uniformity of active materials over a large area and/or incompatibility with conventional microfabrication process for batch device manufacturing (12,(19)(20)(21)(22), integrated flexible memory arrays for system-level applications are still rarely reported. ...
Article
Epidermal electronic systems that simultaneously provide physiological information acquisition, processing, and storage are in high demand for health care/clinical applications. However, these system-level demonstrations using flexible devices are still challenging because of obstacles in device performance, functional module construction, or integration scale. Here, on the basis of carbon nanotubes, we present an epidermal system that incorporates flexible sensors, sensor interface circuits, and an integrated flash memory array to collect physiological information from the human body surface; amplify weak biosignals by high-performance differential amplifiers (voltage gain of 27 decibels, common-mode rejection ratio of >43 decibels, and gain bandwidth product of >22 kilohertz); and store the processed information in the memory array with performance on par with industrial standards (retention time of 108 seconds, program/erase voltages of ±2 volts, and endurance of 106 cycles). The results shed light on the great application potential of epidermal electronic systems in personalized diagnostic and physiological monitoring.
... The recent explosion of information has spawned semiconductor technologies that help to store large amounts of data with a high degree of reliability and high performance at a lower cost with ever smaller form factors. Due to several advantages, including markedly faster read/write speeds, lower power consumption, and no noise, solid-state drivers (SSDs) have become the technology of choice to replace traditional hard disk drives (HDDs) [1][2][3][4][5][6]. An SSD consists of a controller ASIC (Application Specific Integrated Circuit) and a group of flash memory chips. ...
Article
Solid-state drives (SSDs) for mobile and embedded systems may not provide very high performance by today’s standards; however, they are small, low cost and consume little power. SSD controllers are thus designed as DRAM-less chips. SRAM cells created by the IC foundry as a standard module are embedded in the SSD controller as data buffer and can be single-port or two-port. In an SSD controller, more than two IPs simultaneously access the same SRAM, such as the CPU, data interface, and multiflash memory channel. It is thus complicated to exchange data between multiple ports. A new architecture of the multi-port data buffer (M-Buffer) is proposed in this study to solve this problem. M-Buffer is composed of wide SRAM, a smart arbitrator and several interface port logics. The M-Buffer can be designed as a reusable architecture and is small, low cost and consumes little power.
... T ODAY, NAND flash-based solid state drives (SSDs) have become an important part of storage devices because of their better shock resistance, higher I/O throughput, and lower latency compared with hard disk drives (HDDs) [24], [48]. As a different feature, due to an erasebefore-write characteristic of NAND flash memory [4], [47], SSDs perform out-of-place updates. ...
Article
Full-text available
NAND Flash-based solid-state drives (SSDs) have been widely used as secondary storage devices due to their faster access speed, lower power consumption, and higher reliability compared with hard disk drives. However, application I/O performance can be significantly affected by garbage collection (GC) inside SSDs. For example, a GC operation usually moves valid pages from a victim block into a clean block in a serialized manner. Thus, it increases the GC time and affects the application I/O performance. To address this issue, this article presents a preliminary study on a parallel GC scheme for flash-based SSDs. In our scheme, we parallelize valid page migrations during a GC operation to reduce the total GC time. To do this, we first propose a new flash chip architecture that enables valid page migrations in parallel. Second, we collect information such as new addresses for the migration of valid pages by considering the restriction of SSD operations. Finally, we employ multiple worker threads to migrate the valid pages using the collected information in a parallel manner. We implement and evaluate our scheme using Disksim with Microsoft SSD extension. The experimental result shows that the proposed scheme reduces the overall GC time by 70% and 57% on average compared with the existing scheme and a state-of-the-art GC scheme IPPBE, respectively.
... NAND flash memory is becoming one of the most widely used non-volatile memories because of its fast random access performance, shock resistance, and low power consumption [1] [2]. NAND flash memory stores data as the threshold voltage of each flash cell, which is made up of a floating-gate transistor. ...
... S OLID state drives (SSDs) have been widely adopted as a data storage device of the next generation mobile products, micro satellites and data centers due to low power consumption, small form factor, and high reliability [1]- [5]. As technology develops, the data storage density of SSDs has doubled every year [6], and the data storage capacity per a NAND package of the SSD now exceeds 1 Tera-Byte. Due to such a high integration, higher power density needs to be dissipated in the device [7], [8]. ...
Article
Solid State Drives (SSDs) have been widely used in data storage for micro satellites, data centers and mobile products due to their high performance and high reliability. Recently, Samsung Electronics starts to introduce a ball grid array (BGA) non-volatile memory express (NVMe) SSD, which is a combined package of controller and memory units (i.e., DRAM and NAND) into one package. Due to the smaller form factor with high storage densities and multi-functional devices of BGA NVMe SSDs, a thermal issue becomes more important, requiring fundamental understanding of heat dissipation mechanism. Moreover, for applications in micro satellites, thermal analysis of SSDs should be conducted in vacuum environment. Here, we investigate the heat dissipation mechanism in the newly developed BGA NVMe SSD in both the atmosphere and highvacuum conditions. A finite-element-method-based numerical model is developed for the heat transfer analysis and is verified by experiments at various workload conditions.
... Solid-state drives (SSDs) using NAND flash memories have been replacing hard-disk drives (HDDs) because of SSD's faster speed and higher density. [1][2][3][4][5][6] Figure 1 depicts the structure of NAND flash memory cells of the two-dimensional (2D) NAND flash. By applying the appropriate voltage to the control gates, select gates, and bit lines, read=write= erase operations are executed. ...
Article
In order to improve performance of solid-state drives (SSDs), hybrid SSDs have been proposed. Hybrid SSDs consist of more than two types of NAND flash memories or NAND flash memories and storage-class memories (SCMs). However, the cost of hybrid SSDs adopting SCMs is more expensive than that of NAND flash only SSDs because of the high bit cost of SCMs. This paper proposes unique hybrid SSDs with two-dimensional (2D) horizontal multi-level cell (MLC)/three-dimensional (3D) vertical triple-level cell (TLC) NAND flash memories to achieve higher cost-performance. The 2D-MLC/3D-TLC hybrid SSD achieves up to 31% higher performance than the conventional 2D-MLC/2D-TLC hybrid SSD. The factors of different performance between the proposed hybrid SSD and the conventional hybrid SSD are analyzed by changing its block size, read/write/erase latencies, and write unit of 3D-TLC NAND flash memory, by means of a transaction-level modeling simulator.
... [9][10][11] As represented in Table I, SCM and NAND flash have read and write latency gap, and SCM does not require erase operation unlike NAND flash. Due to access unit asymmetry in NAND flash, 12) garbage collection (GC) is required. GC is time consuming operation because it requires valid (live) page copy and block erase. ...
Article
A hybrid of storage class memory (SCM) and NAND flash is a promising technology for high performance storage. Error correction is inevitable on SCM and NAND flash because their bit error rate (BER) increases with write/erase (W/E) cycles, data retention, and program/read disturb. In addition, scaling and multi-level cell technologies increase BER. However, error-correcting code (ECC) degrades storage performance because of extra memory reading and encoding/decoding time. Therefore, applicable ECC strength of SCM and NAND flash is evaluated independently by fixing ECC strength of one memory in the hybrid storage. As a result, weak BCH ECC with small correctable bit is recommended for the hybrid storage with large SCM capacity because SCM is accessed frequently. In contrast, strong and long-latency LDPC ECC can be applied to NAND flash in the hybrid storage with large SCM capacity because large-capacity SCM improves the storage performance.
... Besides, a (8192, 7168) QC-LDPC code using bit-flipping decoding algorithm is also used for comparison. The selection of information length if based on [25,26]. ...
Article
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With the ever-growing storage density, high-speed, and low-cost data access, flash memory has inevitably become popular. Multi-level cell (MLC) NAND flash memory, which can well balance the data density and memory stability, has occupied the largest market share of flash memory. With the aggressive memory scaling, however, the reliability decays sharply owing to multiple interferences. Therefore, the control system should be embedded with a suitable error correction code (ECC) to guarantee the data integrity and accuracy. We proposed the pre-check scheme which is a multi-strategy polar code scheme to strike a balance between reasonable frame error rate (FER) and decoding latency. Three decoders namely binary-input, quantized-soft, and pure-soft decoders are embedded in this scheme. Since the calculation of soft log-likelihood ratio (LLR) inputs needs multiple sensing operations and optional quantization boundaries, a 2-bit quantized hard-decision decoder is proposed to outperform the hard-decoded LDPC bit-flipping decoder with fewer sensing operations. We notice that polar codes have much lower computational complexity compared to LDPC codes. The stepwise maximum mutual information (SMMI) scheme is also proposed to obtain overlapped boundaries without exhausting search. The mapping scheme using Gray code is employed and proved to achieve better raw error performance compared to other alternatives. Hardware architectures are also given in this paper.
... The persistent storage of data provides device-specific potentials to reduce the energy demand. Strategies for low-power flash memories [Tak09] greatly differ from legacy approaches which operate with hard disks (i.e., spinning down hard disks [LS98]). Similar to considerations on time-memory tradeoffs, persistent storage can tradeoff energy demand required for recalculation and storing data persistently. ...
Thesis
Full-text available
Electrical energy is the single most important operating resource to computer systems. Although the energy demand of computers is an invisible system property by itself, the impact of energy demand is omnipresent and obvious in manifold forms of appearance. Sudden system failures (i.e., system breakdowns) and recurrent standard system operations (i.e., system charging) serve as practical examples. Energy demand of hardware components is a physical property of integrated transistor circuits that build our computers today. However, dynamic energy demand at the hardware level is caused by system activities (i.e., processes) at the software level. The analysis and improvement of system software is in focus due to the causal relationship: system software yields challenges and opportunities in equal measure in order to reduce the energy demand of the system at the hardware level. In particular, fine-tuning of system components offers distinct measures to improve the energy efficiency of computer systems. Improvements concern the coherent design of application and system software under consideration of hardware aspects. This thesis presents, implements, and evaluates unique concepts for proactive energy-aware computing on energy-efficient systems-on-a-chip. In particular, it contributes a development method for energy-aware programming that originates in static and dynamic program analysis to support programmers at the design of energy-aware programs. To assist programmers in reducing the energy demand of their programs, the thesis proposes a software-hardware tooling infrastructure that combines energy-aware programming techniques with automatised energy demand analysis at system level. To further reduce the energy demand of computer systems, the thesis implements a process executive at the operating-system level that exploits a priori information at run time to reduce the energy demand of processes. The corresponding cross-layer approach enables the transfer of programmers’ knowledge to the operating system to reduce the energy demand at run time. The thesis is first to combine dynamic program analysis techniques and the automatic creation of program variants to support energy-aware programming at the operating-system level. The distinct combination of application knowledge to identify and set important adjusting screws for the energy efficient operation of a computing system bound to an operating system is claimed to be novel.
... NAND flash memory is one of the most common nonvolatile memories because of the fast speed and the high density. [1][2][3][4] To increase the capacity and reduce the bit-cost of NAND flash memory, memory cell has been scaled down 2,3) and triple-level cell (TLC) NAND flash memory (3 bit=cell) is adopted. 5-7) However, the threshold voltage (V TH ) margins between V TH states in TLC NAND flash memory are narrower than those in single-level cell (SLC) NAND flash memory (1 bit=cell) and multi-level cell (MLC) NAND flash memory (2 bit=cell). ...
Article
This study analyzes the influence of the interval of time (t S-P) between write/erase endurance stress and programming the final data for the data-retention and read-disturb error evaluations in 1X nm triple-level cell (TLC) NAND flash memories. During the interval of time after the write/erase endurance stresses, electrons are de-trapped from the tunnel dielectric. Eventually, the data-retention error decreases in read-"cold" data which is infrequently read. By introducing long t S-P, e.g., 3 h, with round-robin wear-leveling, the bit error rate (BER) of the read-cold data can be decreased by 47%. Moreover, in read-"hot" data which is frequently read, the BER decreases because V TH-down errors are decreased by introducing long t S-P in over 600 read cycles, while the BER does not decrease in case of the smaller read cycles (<600) because V TH-up errors increase during the read operations. This work introduces the mechanism of the V TH-down error in read-"hot" data. The measured BER of the read-hot data decreases by 74% by introducing optimal t S-P with round-robin wear-leveling.
... In recent years, NAND flash memory based solid-state drive (SSD) is widely used for high-performance data storage, such as data center, because NAND flash has advantages of fast write speed and small power consumption compared with hard disk drive (HDD). [1][2][3][4] On the other hand, storage class memory (SCM) such as phase-change random access memory (PRAM) [5][6][7] and resistive RAM (ReRAM) [8][9][10][11][12][13][14][15] is considered as candidates for the next generation data storage because of its improved endurance, performance, and power consumption compared with the NAND flash memory. Particularly, ReRAM shows excellent scalability beyond the 10 nm technology node and the capability of high data storage density due to multi-level cells (MLC) and crosspoint array structure. ...
Article
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... Figure 1 shows an overall architecture of the SSD. [1][2][3] Management tables are stored in the dynamic random access memory (DRAM). User data are stored in the NAND flash array, which has a low bit cost due to the scaling and multi-bit technologies. ...
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Chapter
This chapter discusses how to build dependable nonvolatile memory systems that range from the SD card to high-performance enterprise storage. The nonvolatile memory systems are mainly composed of NAND flash memories because of their high bit density. However, the reliability of the NAND flash memory is degrading along with the memory-cell scaling. Therefore, the adoption of the highly reliable techniques is becoming increasingly important. On the other hand, storage-class memories (SCMs) are attracting much attention because of the higher performance than NAND flash memories. Since the cost is higher than the NAND flash memories, NAND flash/SCM hybrid configuration is developed. Therefore, some of the techniques introduced in this chapter are for the hybrid storage where SCMs are exploited as nonvolatile buffer. Dynamic codeword transition ECC and error-prediction (EP-) low-density parity-check (LDPC) schemes are the techniques related to the error-correcting codes (ECCs). Page-RAID, reverse mirroring (RM), and shift mirroring (SM) are described as redundant arrays of independent disks (RAID). Moreover, data preprocessing techniques such as asymmetric coding and stripe pattern elimination algorithm (SPEA) are introduced. Error recovery (ER) and error masking (EM) schemes are shown as the techniques which cannot be fit into the above classifications. To design dependable nonvolatile systems, techniques should be selectively applied from each layer (ECC, RAID, data preprocessing, and others) to satisfy the cost, performance, and reliability requirements of the application. Therefore, the storage overhead (cost), performance, and the acceptable bit error rate improvement (reliability) are compared among techniques in this chapter.
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With the emergence of wearable or disposable electronics, there grows a demand for a flash memory realizable on various flexible substrates. Nevertheless, it has been challenging to develop a flash memory that simultaneously exhibits a significant level of flexibility and performance. This is mainly due to the scarcity of flexible dielectric materials with insulating properties sufficient for a flash memory, which involves dual dielectric layers, respectively, responsible for tunneling and blocking of charges. Here we report ultra-flexible organic flash memories based on polymer dielectrics prepared by initiated chemical vapor deposition. Using their near-ideal dielectric characteristics, we demonstrate flash memories bendable down to a radius of 300 μm that exhibits a relatively long-projected retention with a programming voltage on par with the present industrial standards. The proposed memory technology is then applied to non-conventional substrates, such as papers, to demonstrate its feasibility in a wide range of applications.
Article
This paper presents a half-select free 9T SRAM to facilitate reliable SRAM operation in the near-threshold voltage region. In the proposed SRAM, the half-select disturbance, which results in instable operations in 6T SRAM cell, can be completely eliminated by adopting cross-access selection of row and column word-lines. To minimize the area overhead of the half-select free 9T SRAM cell, a bit-line and access transistors between the adjacent cells are shared using a symmetric shared node that connects two cells. In addition, a selective pre-charge scheme considering the preferably isolated unselected cells has also been proposed to reduce the dynamic power consumption. The simulation results with the most probable failure point method show that the proposed 9T SRAM cell has a minimum operating voltage (VMIN)$ of 0.45 V among the half-select free SRAM cells. The test chip with 65-nm CMOS technology shows that the proposed 9T SRAM is fully operated at 0.35 V and 25 °C condition. Under the supply voltages between 0.35 and 1.1 V, the 4-kb SRAM macro is operated between 640 kHz and 560 MHz, respectively. The proposed 9T SRAM shows the best voltage scalability without any assist circuit while maintaining small macro area and fast operation frequency.
Article
This paper presents a through-silicon-via (TSV) design methodology for three-dimentional solid-state-drive (3D-SSD) system with the 20 V boost converter. Although TSV technologies give compact packaging and high performance compared to the conventional wire-bonding technology, the parasitic resistors and capacitors of TSVs may cause the performance degradation. Additionally, since the number of the activated NAND chip is dynamically changed as access patterns from real processor, the optimum design point for the boost converter is also moved according to the situation. Then, the clustering method with two different sizes of Cu-TSVs and the adaptive TSV number controlling technique for polycrystalline silicon TSVs are proposed to reduce the parasitic resistors and capacitors. With the cluster structure and Cu-TSVs, the performance of the proposed 3D-SSD is improved by ~10%. Furthermore, the adaptive TSV number controller enhances the performance up to 2 times higher for poly-Si TSV case by reducing the parasitic elements due to TSVs.
Conference Paper
Traditionally, floating gate (flash) transistors have been used exclusively to implement non-volatile memory in its various forms. Recently, we showed that flash transistors can be used to implement digital circuits as well. In this paper, we present the details on the realization and characteristics of the block-level flash-based digital design. The current work describes the synthesis flow to decompose a circuit block into a network of interconnected FCs. The resulting network is characterized with respect to timing, power and energy, and the results are compared with a standard-cell based realization of the same block (obtained using commercial tools). We obtain significantly improved delay (0.59×), power (0.35×) and cell area (0.60×) compared to a traditional CMOS standard-cell based approach, when averaged over 12 standard benchmarks. It is generally rare that a circuit methodology yields results that are better than existing commercial standard-cell based flows in terms of delay, area, power and energy, and in this sense, we submit that our results are significant. Additional benefits of a flash-based digital design is that it allows for precision speed binning in the factory, and also enables in-field re-programmability (we note that our flash-based design is not an FPGA, but rather an ASIC style design) to counteract the speed degradation of a design due to aging. These benefits arise from the fact that the threshold voltage of flash devices can be controlled with precision.
Conference Paper
This paper presents a method to use floating gate (flash) transistors to implement low power ternary-valued digital circuits targeting handheld and IoT devices. Since the threshold voltage of flash devices can be modified at a fine granularity during programming, our approach has several advantages. For one, speed binning at the factory can be controlled with precision. Secondly, an IC can be re-programmed in the field, to negate effects such as aging, which has been a significant problem in recent times, particularly for mission-critical applications. We present the circuit topology that we use in our flash-based ternary-valued logic digital circuit approach, and, through circuit simulations, show that our approach yields significantly improved power (~11%), energy (~29%) and area (~83%) characteristics while operating at a clock rate that is 36% as compared to a traditional CMOS standard cell based approach, when averaged over 20 designs. Unlike CMOS, our ternary-valued, flash-based implementation provides in-field configuration flexibility.
Article
Solid-state drives (SSDs) are rapidly replacing hard disk drives in enterprise data centers due to their higher throughput and reliability. However, the SSD’s random write performance is limited by the NAND flash memories within the SSD, which require garbage collection (GC). To improve the write throughput, a logical block address (LBA) scrambler has been previously proposed. However, there are two issues associated with this solution. First, with the LBA scrambler, SSD throughput actually worsens for some types of workloads, such as prxy_0. Second, a large table size is needed. In this paper, the first problem is solved by a write order (WO)-based GC scheme. In order to choose the victim block, the parameters of valid page ratio, write order, and erase count of the NAND flash blocks are collectively considered according to a new formula. A key advantage of utilizing the relative write order of the blocks is that an internal timer is not needed to monitor the ages of the blocks. Second, a sector bundling scheme is proposed to reduce the table size of the LBA scrambler. Based on the experimental results, with the two proposals, SSD throughput is improved by 2.4 times, and the table size of the LBA scrambler is reduced by 45%.
Chapter
This chapter introduces the design of three-dimensional (3D) NAND flash memory with the implications from the system side. For conventional two-dimensional (2D) scaling, it is facing various limitations such as lithography cost and cell-to-cell coupling interference. To sustain the trend of bit-cost reduction beyond 10 nm technology node, 3D NAND flash memory is considered as the next generation technique. Further, emerging memories called storage-class memories (SCMs) such as resistive RAM (ReRAM), phase change RAM (PRAM) and magnetoresistive RAM (MRAM) will revolutionize the storage system design. By introducing SCM into the solid-state drive (SSD), hybrid SCM/3D-NAND flash SSD and all SCM SSD achieve much higher write performance than all 3D-NAND flash SSD due to SCM’s fast speed. In addition, the performance of the SSD is workload dependent. Thus, it is meaningful to obtain the design guidelines of 3D NAND flash for both all 3D-NAND flash SSD and hybrid SCM/3D-NAND flash SSD with representative real-world workloads.
Article
A solid-state drive (SSD) with 1Xnm triple-level cell (TLC) NAND flash is proposed for low cost data storage applications with long-term data-retention requirements. Specifically, cold data storage requires 20 years data-retention with 100 write/erase (W/E) cycles, whereas digital archive storage requires 1000 years retention time with 1 W/E cycle. To achieve these requirements, a flexible-nLC scheme is proposed to improve the reliability of 1Xnm TLC NAND flash (Yamazaki et al., 2015). The proposed scheme combines two schemes, n-out-of-8 level cell (nLC) (Tanakamaru et al., 2014) and asymmetric coding (AC) (Tanakamaru et al., 2012) with the addition of a vertical flag. By measuring 1Xnm TLC NAND flash memory, the proposed scheme reduces errors by 72% and 69% for digital archive and cold flash respectively, compared to the conventional nLC scheme.
Article
Solid State Drive (SSD) for the consumer market may not require extreme high performance, but it does want high density at a low cost. Redundant Array of Inexpensive (or Independent) Disks (RAID) are built up by a group of independent disk drives, not inside a disk drive. This makes a RAID system not as inexpensive as expected in the beginning and in the end the system often becomes expensive, large in size and complexity. It is not well suited for consumer applications. This paper proposes a new structure, to build up a high density SSD in a RAID system by using SD or MMC/ eMMC modules instead of independent drives. A SSD controller chip with embedded RAID (eRAID) multiple level functions was designed and applied to verify this proposal. By using this controller and eMMC modules, a redundant array of independent modules (RAIM) is built up as an inexpensive single drive and proven to work. The result revealed that a RAIM can be a single SSD drive as well as a micro-RAID system. By utilizing RAIM SSD units a more sophisticated RAID system can be constructed at lower costs and greater performance in a much smaller configuration, which is more suitable as home cloud storage, etc.
Article
NAND flash based storage devices adopts multi-channel and multi-way architecture to improve performance using parallel operation of multiple NAND devices. However, multiple NAND devices consume higher current and peak power overlap problem influences on the system stability and data reliability. In this paper, current waveform is measured for erase, program and read operations, peak current and model is defined by profiling method, and estimated probability of peak current overlap among NAND devices. Also, system level TLM simulator is developed to analyze peak overlap phenomenon depending on various simulation scenario. In order to remove peak overlapping, token-ring based simple power management method is applied in the simulation experiments. The optimal peak overlap ratio is proposed to minimize performance degradation based on relationship between peak current overlapping and system performance.
Article
With highly scaled 40 or 30 nm technologies, the memory capacity increases to as much as 32 Gbit as shown in Fig. 18.1. By using gigabit-capacity NAND flash memories, SSD, Solid-State Drive that uses NAND as a mass storage of personal computers and enterprise servers is expected as a next killer application of NAND Flash memories.
Article
This paper presents a Ternary Content-addressable Memory (TCAM) design which is based on the use of floating-gate (flash) transistors. TCAMs are extensively used in high speed IP networking, and are commonly found in routers in the internet core. Traditional TCAM ICs are built using CMOS devices, and a single TCAM cell utilizes 17 transistors. In contrast, our TCAM cell utilizes only 2 flash transistors, thereby significantly reducing circuit area. We cover the chip-level architecture of the TCAMIC briefly, focusing mainly on the TCAMblock which does fast parallel IP routing table lookup. Our flash based TCAM block is simulated in SPICE, and we show that it has a significantly lowered area compared to a CMOS based TCAMblock, with a speed that can meet current (∼400 Gb/s) data rates that are found in the internet core.
Article
This paper presents a Ternary Content-addressable Memory (TCAM) design which is based on the use of floating-gate (flash) transistors. TCAMs are extensively used in high speed IP networking, and are commonly found in routers in the internet core. Traditional TCAM ICs are built using CMOS devices, and a single TCAM cell utilizes 17 transistors. In contrast, our TCAM cell utilizes only two flash transistors, thereby significantly reducing circuit area. We cover the chip-level architecture of the TCAM IC briefly, focusing mainly on the TCAM block which does fast parallel IP routing table lookup. Our flash-based TCAM (FTCAM) block is simulated in SPICE, and we show that it has a significantly lowered area compared to a CMOS based TCAM block, with a speed that can meet current (∼ 400 Gb/s) data rates that are found in the internet core.
Article
Currently, solid-state drives (SSDs) are replacing hard-disk drives (HDDs) in many applications. However, SSDs write performance is low because of the NAND flash memory's characteristics. Particularly, the garbage collection (GC) page-copy overhead for the valid data greatly degrades the SSD performance. To suppress this overhead with the address remapping technology, a middleware, LBA scrambler, is proposed [3]. We evaluated the effects of the LBA scrambler with the Ext4 file system (FS). From the experimental results, the SSD performance is boosted by 20.0% with the assistance of the LBA scrambler, compared with the conventional system without LBA scrambler. Moreover, the total SSD energy consumption is reduced by 4.33% while its lifetime is enhanced by 3.56%.
Article
Solid-state drives (SSDs) are over-taking hard disk drives (HDDs) as high-volume storage in enterprise servers and data centers. However, SSDs write performance is limited due to their inability to overwrite in-place and need for garbage collection. To reduce the garbage collection (GC) overhead, a logical block address (LBA) scrambler has been proposed. However, the LBA scrambler has two issues: (1) SSD performance decreases with a hot and random workload, and (2) the table size of the LBA scrambler may become upto 0.85% of the SSD capacity. In this work, a write order (WO) based GC scheme is proposed to solve the first issue. The number of valid pages in the NAND flash block, the write order and erase count of the block are considered for victim block selection during GC. One of the key advantages of the WO GC is that it does not require a clock inside the SSD, which will not operate if the SSD power is off. Further, to solve the second issue of the large table size, a Sector Bundling scheme is proposed. From the results, SSD performance is improved 3×, and the LBA scrambler table size is reduced 16%.
Article
Hybrid films of pentacene and aluminum nanoparticles were prepared by depositing pentacene on a SiO 2 surface decorated with aluminum nanoparticles and used as the active channel materials in a thin film transistor. Surface pre-treatment of the aluminum nanoparticles with oxygen plasma and/or organophosphonic acids render the particles surface with different coatings and work functions, which affect the charge trapping/storing ability of the nanoparticles. This in turn results in an electric bistability of the pentacene film-based transistor/memory devices. Correlations of memory window, switching response, and memory retention characteristics with the aluminum nanoparticle surface treatment are provided.
Article
Rank modulation is a new data representation method, which can be used for flash memory devices and other types of nonvolatile memory devices. This innovative technology does not use absolute values of cell levels, but instead uses relations in a group of memory elements. However, to establish rank modulation memory as a practical memory device, efficient and reliable rank determination (read circuitry) must be designed, and the characteristics of the rank modulation memory have to be explored with extensive research and experimental tests. This brief presents a rank modulation memory device, which was fabricated in a 0.35- $mumathrm{m}$ CMOS process. Rank read circuitry with the current-comparing scheme was integrated into the IC, and the rank determination ability was tested. In addition, retention tests were performed to explore how the level changes affect cell ranks in an array of memory cells.
Article
Wear-leveling algorithm is one of the key technologies in optimizing the endurance as well as the performance for a NAND flash memory-based system. An efficient wear-leveling algorithm, based on the combination method of the block-mapping table and page-mapping table with only very limited on-chip buffer resource, is proposed in this paper. This algorithm has excellent power-cycle reliability, and is flexible for those embedded digital storage applications in which the on-chip buffer resource for mapping table and data buffer is limited. For those applications, any additional memory chip applied as large mapping table or payload data buffer space is not accepted, considering the form-factor size or material cost. A real silicon chip, as a NAND flash controller without auxiliary buffer, was realized to apply this algorithm. Its efficiency and performance have been silicon-proven.
Article
A cell design for three-dimensional (3D) stackable NAND (3D NAND) flash memory are investigated with emphases on control gate length (L-g), spacing (L-space) and channel hole diameter (phi). The requirements for the L-g and L-space derived from the 3D device simulation and the effective cell size that competes with the planar NAND. The simulations reveal that L-g = L-space = 20 nm (40 nm layer pitch) is achievable for bit-cost scalable (BICS)-type 3D NAND with the 90 nm diameter hole. If the number of stacked layers s 22 with the layer pitch of 40 nm, the effective cell size of the 3D NAND corresponds to that of 15 nm planar NAND technology. Furthermore, characteristics of the macaroni body channel with various phi are investigated. Although macaroni body channel improves cell characteristics at phi = 90 nm, a cell with phi = 60 nm without macaroni body structure shows better characteristics. (C) 2014 The Japan Society of Applied Physics
Article
A 1G-cell NOR flash memory chip has been designed and fabricated successfully with 65 nm technology. To compromise the array efficiency and chip speed, the paper establishes an array model including parasitics of the whole array, and optimizes the sector structure as 512 wordlines (WLs) and 4096 bitlines (BLs). Furthermore, by adding other models of long and thin metal lines, we have analyzed the speed of critical circuit nodes. As a result, the agreement of WL delay between simulation and measurement verifies the accuracy of the array model and lines models. The test results indicate that the chip achieves random access time of 100 ns and page read time of 25 ns under 3.3 V voltage supply.
Article
There is an increasing demand for the solid-state drive (SSD) due to its high speed, low power, and high reliability. However, random write intensive workload is not good for the SSD performance due to the inherent characteristics of the NAND flash memory. As the garbage collection (GC) causes the bottleneck of the SSD write performance due to the page-copy overhead, a NAND flash aware system is proposed to improve the SSD performance with a scheme called logical block address (LBA) scrambler. In the proposed scheme, new data are actively written to the fragmented pages in the next erase block. As a result, the number of valid pages inside the block is reduced when the block is recycled. Considering that there are NAND flash blocks full of valid pages in the proposed scheme, a skipping full block round robin (SFB_RR) GC policy is proposed, showing 0%-58% performance improvement compared with the RR GC policy. Furthermore, certain valid pages in the SSD have obsolete data due to the logical address remapping of the LBA scrambler, which cannot be invalidated by the conventional TRIM command, thus a SWEEP command is introduced. With the SWEEP command, maximum 12% additional SSD performance gain is obtained. From the experimental results, 35%-394% performance improvement, 27%-56% energy consumption reduction, and 25%-55% endurance enhancement are achieved by the proposed LBA scrambler scheme + SFB_RR GC policy + SWEEP command support, compared with the conventional SSD.
Article
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Emerging application areas of mass storage flash memories require low cost, high density flash memories with enhanced device performance. This paper describes a 64 Mb NAND flash memory having improved read and program performances. A 40 MB/s read throughput is achieved by improving the page sensing time and employing the full-chip burst read capability. A 2-μs random access time is obtained by using a precharged capacitive decoupling sensing scheme with a staggered row decoder scheme. The full-chip burst read capability is realized by introducing a new array architecture. A narrow incremental step pulse programming scheme achieves a 5 MB/s program throughput corresponding to 180 ns/Byte effective program speed. The chip has been fabricated using a 0.4-μm single-metal CMOS process resulting in a die size of 120 mm<sup>2</sup> and an effective cell size of 1.1 μm<sup>2</sup>
Conference Paper
The authors describe a technology for scaling down the flash EEPROM cell, which has a conventional self-aligned double poly-Si stacked structure. It is clarified experimentally that a flash memory cell written and erased by Fowler-Nordheim (F-N) tunneling has ten times the retention time of the conventional cell, which is written by channel-hot-electron (CHE) injection and erased by F-N tunneling. This difference of data retentivity between these two write/erase (W/E) technologies is due to decreasing the thin gate oxide leakage current by bi-polarity F-N tunneling stress. This improvement in data retention becomes more pronounced as the gate oxide thickness decreases. Therefore, a bipolarity F-N tunneling WE technology, which enables a flash EEPROM cell to scale down its oxide thickness, shows promise as a key technology for realizing 16 Mb flash EEPROMs and beyond
Article
A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3) chip published with all-bitline (ABL) architecture, which doubles the write performance compared with conventional shielded bitline architecture. A new advanced cache program algorithm provides another 15% improvement in write performance. This paper also discusses a technique for resolving the sensing error resulting from cell source line noise, which usually varies with the data pattern. The new architecture and advanced algorithm enable an 8 MB/s write performance that is comparable to previously published 2-bit per cell (4-level) NAND performance. Considering the significant cost reduction compared to 4-level NAND flash based on the same technology, this chip is a strong candidate for many mainstream applications.
Conference Paper
NAND flash memory use in digital still cameras and cellular phones is driving demand for larger-capacity storage. Moreover, NAND flash has the potential to replace HDDs. To achieve larger capacity while maintaining low cost per bit, technical improvements in feature size and area reduction are essential. To meet the stringent requirements, we develop a 16 Gb 4-level NAND flash memory in 43 nm CMOS technology. In 43 nm generation, gate-induced drain leakage (GIDL) influences the electrical field on both sides of NAND strings. GIDL causes severe program disturb problems to NAND flash memories. To avoid GIDL, two dummy wordlines (WL) on both sides of NAND strings are added. This is effective because the dummy gate voltages, are selected independent of the program inhibit voltage.
Conference Paper
Three new circuit technologies, selective bit-line precharge scheme, advanced source-line program, and intelligent interleaving are proposed. By co-designing NAND flash memory and NAND controller circuits, both NAND and NAND controllers are best optimized. At sub-30 nm generation, the SSD speed improves by 150% without a cost penalty or circuit noise.
Conference Paper
A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed. This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash with the same design rule. New programming method achieves 0.62 MB/s programming throughput.
Conference Paper
NAND flash memory based solid-state disk (NSSD) has been used for industrial and military use due to its high reliability and shock resistance. With the bit cost reduction of flash memory and the explosive growth of flash market, NSSD is expected to penetrate into diverse applications such as mobile thin clients, car navigation systems and movie players, which prefer low power consumption, high reliability, high performance and so on. This paper mainly focuses on the development of a high performance and cost-efficient controller for NSSD, with the aim of describing both hardware and software architectures. In order to demonstrate the usefulness of the proposed approach, we show performance, power consumption and start-up time evaluation results over magnetic disks using third party benchmark tools
Conference Paper
A 146 mm<sup>2</sup> 8 Gb NANO flash memory with 4-level programmed cells is fabricated in a 70 nm CMOS technology. A single-sided pad architecture and extended block-addressing scheme without redundancy is adopted for die size reduction. The programming throughput is 6 MB/s and is comparable to binary flash memories.
Conference Paper
In order to realize ultra high density EPROM and Flash EEPROM, a NAND structure cell is proposed. This new structure is able to shrink cell size without scaling of device dimensions. The NAND structure cell realizes a cell as small as 6.43 µm<sup>2</sup>using 1.0 µm design rule. As a result, cell area per bit can be reduced by 30% compared with that of a 4M bit EPROM using the conventional structure and the same design rule. It is confirmed that each bit in a NAND cell is able to be programmed selectively. This high performance NAND structure cell is applicable to high density nonvolatile memories as large as 8M bit EPROM and Flash-EEPROM or beyond.
Conference Paper
The increasing demand for low voltage/low power portable equipment in the consumer marketplace has created a need for a low voltage/low power flash memory. In portable communication products, sub-1.8 V operation is essential. In view of the chip cost, a NAND-type cell has a big advantage over a NOR-type cell due to its smaller cell size. However, in this paper we show for the first time that the conventional NAND flash memory cannot operate below 2.0 V due to a program disturb issue. To solve this problem, we propose a new programming scheme which drastically reduces the program disturb and realizes highly reliable, high-speed programming, low voltage operation, low power consumption and low cost NAND flash memories
Conference Paper
This paper first explains that gate array noise during a bit-by-bit program verify operation, named source line noise, is estimated to have a crucial adverse effect on the threshold voltage (V <sub>th</sub>) control and causes a serious problem in Multi-Level NAND Flash Memories. Then a new array architecture, a Double-Level-V<sub>th </sub> Select Gate Array Architecture, is introduced to eliminate this noise without cell area penalty
Conference Paper
Due to their small cell size, low power consumption, and fast page based read/program operations, NAND type flash memories are well suited for portable mass storage. This 3.3 V only 32 Mb NAND flash memory achieves typical 2.3 MB/s program performance with an incremental step pulse programming (ISPP) scheme. In addition, self-boosting of program inhibit voltages lowers the page programming current to 4.3 mA and a 24 MB/s read throughput is achieved with interleaved data paths. The device is fabricated in a 0.5 μm CMOS process on a 94.9 mm<sup>2</sup> die
Conference Paper
A quick program/program verify architecture with an intelligent verify circuit for 3-V-only NAND-EEPROMs is described. The verify circuit, which is composed of two transistors, provides a simple, intelligent program algorithm for 3-V-only operation. The total programming time is reduced to 50%. By using intelligent verify circuits, the memory cells which require more time to reach the program state are automatically detected. Verify-read, the modification of program data, and data reload are performed simultaneously. The chip size penalty is estimated to be only 1% for a 16-Mb NAND-EEPROM
Article
A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.
Article
A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm<sup>2</sup>, has been successfully developed. This is the world's first integrated semiconductor chip fabricated with 56-nm CMOS technologies. The effective cell size including the select transistors is 0.0075 mum<sup>2</sup> per bit, which is the smallest ever reported. To decrease the chip size, a very efficient floor plan with one-sided row decoder, one-sided page buffer, and one-sided pad is introduced. As a result, an excellent 70% cell area efficiency is realized. The program throughput is drastically improved to twice as large as previously reported and comparable to binary memories. The best ever 10-MB/s programming is realized by increasing the page size from 4kB to 8kB. In addition, noise cancellation circuits and the dual VDD-line scheme realize both a small die size and a fast programming. An external page copy achieves a fast 93-ms block copy, efficiently using a 1-MB block size
Article
To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 μs/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme
Article
To realize low-cost, highly reliable, high-speed programming, and high-density multilevel flash memories, a multipage cell architecture has been proposed. This architecture enables both precise control of the V<sub>th</sub> of a memory cell and fast programming without any area penalty. In the case of a four-level cell, a high programming speed of 236 μs/512 bytes or 2.2 Mbytes/s can be obtained, which is 2.3 times faster than the conventional method. A small die size can be achieved with the newly developed compact four-level column latch circuit. A preferential page select method has also been proposed so as to improve the data retention characteristics. The IC error rate can be decreased by as much as 33%, and a highly reliable operation can be realized
Article
In multilevel flash memories, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new array architecture, “A double-level-V<sub>th</sub> select gate array architecture” to eliminate the array noise, together with a reduction of the cell area. The array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional array. In the proposed array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed array and a reliable operation of a multilevel NAND flash memory can be realized
Article
While the performance of flash memory exceeds hard disk drives in almost every category, the cost of flash memory must come down in order to gain wider acceptance in mass storage applications. This paper describes a 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm<sup>2</sup> die size, improved yields, and a simple process with 0.5 μm CMOS technology. Die size is reduced by eliminating high voltage operation on the bitlines through a self boosted program inhibit voltage generation scheme. Incremental-step-pulse programming results in a 2.3 MB/s program data rate as well as improved process variation tolerance. Interleaved data paths and a boosted wordline results in a 25 ns burst cycle time and a 24 MB/s read data rate. Maximum operating current is less than 8 mA
A 16 Gb 3b/cell NAND flash memory in 56 nm with 8 MB/s write rate
  • Y Li
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NAND successful as a media for SSD
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A high performance controller for NAND flash-based solid state disk (NSSD)," in NVSMW Tech
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A 56 nm CMOS 99 mm 8 Gbit multi-level NAND flash memory with 10 Mbyte/sec program throughput
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A 120 mm 16 Gb 4-MLC NAND flash memory with 43 nm CMOS technology
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K. Kanda et al., "A 120 mm 16 Gb 4-MLC NAND flash memory with 43 nm CMOS technology," in IEEE ISSCC Dig., 2008, pp. 430-431.
A reliable bi-polarity write/erase technology in flash EEPROMs
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New ultra high density EPROM and flash EEPROM with NAND structured cell
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