An LC-Based Clock Buffer With Tunable Injection Locking

NetLogic Microsyst., Mountain View, CA
IEEE Journal of Solid-State Circuits (Impact Factor: 3.01). 04/2009; 44(3):797 - 807. DOI: 10.1109/JSSC.2008.2011040
Source: IEEE Xplore


This paper introduces a hybridized version of two common topologies of LC-based clock buffers. The proposed design can minimize jitter by adaptively adjusting the ratio between these two topologies. The analysis shows that the setting for optimum jitter depends on the relative level between the input noise and the inherent noise of the clock buffer. The long-term and short-term jitters are both studied and supported by measurement. A frequency tuning technique based on a voltage-swing digitizer is also demonstrated. The test chip is fabricated in a 1P8M 1.2-V 0.13-mum digital CMOS process. The power consumption of the proposed LC-based clock buffer is 12 mW.

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    ABSTRACT: A novel technique for wideband injection locking in an LC oscillator is proposed. PLL and injection locking elements are combined symbiotically to achieve wide locking range while retaining the simplicity of the latter. This method doesn't require a phase frequency detector or a loop filter to achieve phase lock. 13.4GHz - 17.2GHz locking range and an average jitter tracking bandwidth of up to 400 MHz was measured in a high-Q LC oscillator. This architecture is used to generate quadrature phases form a single clock without any frequency division, and to provide high frequency jitter filtering while retaining the low frequency correlated jitter essential for clock forwarded receivers.
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