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Cramming more components onto integrated circuits, Reprinted from Electronics, volume 38, number 8, April 19, 1965, pp.114 ff
Abstract
Moore's theories about the future of transistor technology first appeared in Electronics magazine in April 1965. Termed a "law" years later by Caltech professor Carver Mead, Moore's Law went on to become a self-fulfilling prophecy.
... Lithography is one of the most critical processes in semiconductor manufacturing [1]. The advancement of lithography technology has enabled the continuous extension of Moore's Law, leading to a constant reduction in device size, and consequently, higher integration levels, and better circuit performance [2]. According to the Rayleigh criterion [1], the minimum feature size that a system can resolve is determined by Eq. (1): ...
Extreme ultraviolet (EUV) lithography is one of the most indispensable technologies in semiconductor manufacturing for 7 nm and smaller technology nodes. However, many key parameters in the lithography system may deviate from target values, and there are extremely complex coupling effects among these parameters. Additionally, aberrations that far exceed expectations damage lithography results severely. These accidents pose significant challenges in achieving satisfactory lithography outcomes. To investigate the impact of aberrations coupled with multiple key parameters on lithography results, and to provide quantitative and precise direction for the research and development of lithography systems, this paper proposes a methodology of budget analysis of aberrations based on probability distribution. First, a rapid prediction model of lithography results is established by multilayer perceptron. Then, the lithography results under different parameter conditions are obtained according to the prediction model. Subsequently, the aberration combinations that meet lithography requirements are filtered out. Finally, the impact of each aberration on lithography results and their budget range can be determined according to the general distribution and joint probability distribution of aberrations coupled with multiple key parameters. For patterns commonly used in EUV single exposure at the 5 nm technology node, this paper finds that aberrations such as Z2 and Z4 exhibit significant impacts on lithography results under the coupling of multiple key parameters. Additionally, all the budget ranges of aberrations are obtained. Specifically, for example, Z2, Z4, and Z5, their budget ranges are -18∼15mλ, 10∼45mλ, 7∼43mλ, respectively. While items such as Z1 and Z27, their budget ranges are -40∼40mλ consistently. This method can obtain the impact and budget range of aberrations under the coupling of multiple key parameters in the lithography system quickly and accurately. It can provide a reliable guideline for aberration compensation and optimization, and the research and development of lithography systems. Moreover, the budget ranges obtained by this method can also serve as a clear indicator for aberration monitoring.
... Downscaling, the relentless size reduction approach to enhance the performance of field-effect transistors (FETs), has fueled the phenomenal progress in computing integrated circuit (IC) technology (Moore's law) for the past 50 years. [1][2][3][4][5][6][7][8][9] However, the physical device limitations concomitant with extreme downscaling and its prohibitive fabrication cost are great obstacles ushering the demise of such a paradigm. [9][10][11] Due to the urgent need 11 of overcoming the diminishing returns and cost of continuing device downscaling, many "beyond CMOS" devices are being pursued, which exploit various physical phenomena, such as 9,12 (1) particle (electron/hole) charge manipulation (e.g., the Tunneling FET (TFET), the graphene PN junction, and the bilayer pseudo-spin-FET; (2) electron spin manipulation (e.g., the spinFET); (3) magnetic domain wall manipulation (e.g., the spin transfer torque/domain wall device); (4) spin wave manipulation (e.g., the spin wave device); and (5) magnetic coupling manipulation (e.g., nanomagnetic logic and probabilistic spin logic). ...
We report the experimental demonstration of plasmon–plasmon scattering at room temperature in the inversion layer of a patterned metal–oxide–semiconductor structure. This fundamental result paves the way for the development of plasmon–plasmon scattering logic, a revolutionary digital logic concept based on the generation, propagation, and manipulation of plasmons in an electron fluid, which was previously theoretically projected to exhibit femtojoule power dissipations and femtosecond switching speeds, while not demanding expensive nanometer-scale silicon (Si) technology fabrication processes for its implementation.
... N order to sustain the scaling process of the MOS technology predicted by Moore's law, which demonstrates that the number of transistors in a chip doubles every two years, the semiconductor industry searches for ways to reduce the transistor dimensions to enhance the circuits' performance and to reduce the cost per executed function [1]. The reduction of the device's dimensions is not always followed by the decrease of the applied potentials, which can cause an increase in the internal electric fields in the structure and in the power density, mainly in integrated circuits where a considerable number of devices operate simultaneously [2]. ...
This work aims to perform a comprehensive comparison of the electrical properties of junctionless and inversion-mode nanowires MOSFETS, fabricated with similar gate stack and state-of-art process, in the temperature range from 300 K to 580 K. The comparative analysis is performed through the main electrical parameters of the devices, such as the threshold voltage, subthreshold current and slope, DIBL, conduction current, mobility, and maximum transconductance extracted from experimental data. Devices with different fin widths are compared. It is demonstrated that the inversion-mode nanowire transistors present higher performance with three times higher maximum transconductance and conduction current and twice higher low field mobility than the junctionless’ with a fin width of 10 nm at a fixed temperature. On the other hand, the junctionless nanowire transistors presented higher thermal stability of their electrical parameters with a 75% lower variation of maximum transconductance with temperature, 77% lower maximum transconductance variation with temperature, and 22% lower temperature coefficient of mobility.
Providing the reader with an up-to-date digest of the most important current research carried out in the field, this volume is compiled and written by leading experts. This volume reviews the trends in electrochemical sensing and its application and touches on research areas from a diverse range, including electrochemical detection of infectious pathogens, hybrid materials for electrocatalysis and photoelectrocatalysis, chip fabrication from an electrochemical perspective and exploring forensic mysteries with electrochemical sensors, to name just a few.
Coverage is extensive and will appeal to a broad readership from chemists and biochemists to engineers and materials scientists. The reviews of established and current interest in the field make this volume a key reference for researchers in this exciting and developing area.
Two-dimensional (2D) dielectrics, integrated with high-mobility semiconductors, show great promise to overcome the scaling limits in miniaturized integrated circuits. However, the 2D dielectrics explored to date still face the challenges of low crystallinity, diminished dielectric constant, and the lack of effective synthesis methods. Here, we report the controllable synthesis of ultra-thin gadolinium oxychloride (GdOCl) nanosheets via a chloride hydrate-assisted chemical vapor deposition (CVD) method. The resultant GdOCl nanosheets display good dielectric properties, including a high dielectric constant (high-κ) of 15.3, robust breakdown field strengths (Ebd) exceeding 9.9 MV/cm, and minimal gate leakage currents of approximately 10⁻⁶ A/cm². The top-gated GdOCl/MoS2 field-effect transistors (FETs) exhibit commendable switch characteristics, a negligible hysteresis of ~5 mV and a subthreshold swing down to 67.9 mV dec⁻¹. The GdOCl/MoS2 FETs can also be employed to construct functional logic gates. Our study underscores the significant potential of the 2D GdOCl dielectric for innovative high-speed operated nanoelectronic devices.
Ge two-dimensional hole gases in strained modulation-doped quantum-wells represent a promising material platform for future spintronic applications due to their excellent spin transport properties and the theoretical possibility of efficient spin manipulation. Due to the continuous development of epitaxial growth recipes extreme high hole mobilities and low effective masses can be achieved, promising an efficient spin transport. Furthermore, the Ge two-dimensional hole gas (2DHG) can be integrated in the well-established industrial complementary metal-oxide-semiconductor (CMOS) devices technology. However, efficient electrical spin injection into a Ge 2DHG – an essential prerequisite for the realization of spintronic devices - has not yet been demonstrated. In this work, we report the fabrication and low-temperature magnetoresistance measurements of a laterally structured Mn5Ge3/Ge 2DHG/ Mn5Ge3 device. The ferromagnetic Mn5Ge3 contacts are grown directly into the Ge quantum well by means of an interdiffusion process with a spacing of approximately 130 nm, forming a direct electrical contact between the ferromagnetic metal and the Ge 2DHG. Here, we report for the first time a clear magnetoresistance signal for temperatures below 13 K possibly arising from successful spin injection into the high mobility Ge 2DHG. The results represent a step forward toward the realization of CMOS compatible spintronic devices based on a 2DHG.
Pointers are an integral part of C and other programming languages. They enable substantial flexibility from the programmer’s standpoint, allowing the user fine, unmediated control over data access patterns. However, accesses done through pointers are often hard to track, and challenging to understand for optimizers, compilers, and sometimes, even for the developers themselves because of the direct memory access they provide. We alleviate this problem by exposing additional information to analyzers and compilers. By separating the concept of a pointer into a data container and an offset, we can optimize C programs beyond what other state-of-the-art approaches are capable of, in some cases even enabling auto-parallelization. Using this process, we are able to successfully analyze and optimize code from OpenSSL, the Mantevo benchmark suite, and the Lempel–Ziv–Oberhumer compression algorithm. We provide the only automatic approach able to find all parallelization opportunities in the HPCCG benchmark from the Mantevo suite the developers identified and even outperform the reference implementation by up to 18%, as well as speed up the PBKDF2 algorithm implementation from OpenSSL by up to 11x.
Reversible logic circuits are an exciting solution for designing efficient sequential and combinational circuits. Reducing the size of transistors to nanoscale has created new challenges and issues in the field-effect transistor (FET) industry, so alternative technologies are needed. Quantum dot cellular automata (QCA) technology, reversibility, and multi-valued logic can reduce energy loss and occupied area in circuit design. QCA is a new method to design logic circuits in nanotechnology, emerging with nanoelectronics to make more comprehensive and complex logic circuits. In an irreversible logic system, some bits are erased when the system performs any computation, and this causes heat dissipation and energy loss. Using reversible ternary logic instead of previous technologies leads to better performance and saving more energy. In this paper, we proposed a design for ternary quantum dot cellular automata (TQCA) reversible T flip-flop. For the first time, we have proposed circuits that simultaneously combine ternary logic, reversibility, and implementation using ternary QCA technology. Reversible gates are the basis of a reversible circuit, which is implemented in this paper to create a TQCA Toffoli gate and reversible fan-out circuit as the fundamentals of TQCA T flip-flop. In general, T flip-flops are used to implement other more complex sequential circuits, such as counters. The area, delay, cost, and cell count of the proposed TQCA reversible T flip-flop design are compared with those of other related works in binary QCA technology. The occupied area of the proposed TQCA reversible T flip-flop is 0.06 µm2 which is %40 less than that of previous related works.
Laser-produced gadolinium plasma (Gd-LPP) emerges as a promising candidate for next-generation nanolithography light sources. In this study, a dual laser pulse scheme was implemented to achieve a narrow spectral peak. By varying the pre-main pulse delay and pre-pulse laser energy, optimal conditions of 40 ns delay and 50 mJ energy were identified to improve spectral purity. Radiation hydrodynamics simulations revealed that the improved spectral purity stems from a flatter density gradient at the ablation front and a lower average electron density in the EUV emission region. Additionally, reheating the pre-formed plasma with a short main pulse mitigated plasma squeezing, resulting in an even lower electron density and thus improved spectral purity. Our findings suggest that spectral narrowing in the dual-pulse scheme, essential for better matching with multilayer reflection bandwidths, can be optimized through precise control of pre-pulse energy, pre-main delay, and main-pulse duration.
Content Addressable Memories (CAMs) are high-speed hardware lookup tables that are crucial in routing, packet classification, search, and other fast look-up applications. Despite having the advantage of high speed, they have limitations due to their power hungriness. This paper addresses the limitations of existing CAMs with two novel modifications in the proposed Search Line Pre-Charge-Free Low-Power-Content Addressable Memory (SLPFCAM) structure. The first novelty is their gated evaluation matching circuit and the second is a match line pre-charge controller. The proposed design reduces the energy consumption and improves the speed of the CAM by eliminating the SLprecharge phase in the CAM operation. The pre-charge controller prevents the attempt of match line pre-charge when it is not required. The design has been implemented using Cadence Virtuoso in a 90-nm CMOS technology with 1-V supply, and the post-layout simulation results show that the SLPFCAM makes significant improvements with a minimum of 83% less power consumption, a 91% less search delay, and the average energy consumption being 0.765 fJ/bit/search.
Precise event detection within time‐series data is increasingly critical, particularly in noisy environments. Reservoir computing, a robust computing method widely utilized with memristive devices, is efficient in processing temporal signals. However, it typically lacks intrinsic thresholding mechanisms essential for precise event detection. This study introduces a new approach by integrating two Pt/HfO2/TiN (PHT) memristors and one Ni/HfO2/n‐Si (NHS) metal‐oxide‐semiconductor capacitor (2M1MOS) to implement a tunable thresholding function. The current‐voltage nonlinearity of memristors combined with the capacitance‐voltage nonlinearity of the capacitor forms the basis of the 2M1MOS kernel system. The proposed kernel hardware effectively records feature‐specified information of the input signal onto the memristors through capacitive thresholding. In electrocardiogram analysis, the memristive response exhibited a more than ten‐fold difference between arrhythmia and normal beats. In isolated spoken digit classification, the kernel achieved an error rate of only 0.7% by tuning thresholds for various time‐specific conditions. The kernel is also applied to biometric authentication by extracting personal features using various threshold times, presenting more complex and multifaceted uses of heartbeats and voice data as bio‐indicators. These demonstrations highlight the potential of thresholding computing in a memristive framework with heterogeneous integration.
In this work, we present a physical understanding and a robust surface potential coupling relationship essential to accurately capture the transconductance in body-contacted (BC) dynamically depleted silicon-on-insulator (DDSOI) MOSFETs for varied body biases. It is observed that the crossover of transconductance for varied body biases occurs before the peak transconductance is reached for devices operating particularly in the saturation region. This phenomenon is investigated in detail and attributed to partial-depletion-to-full-depletion transition in the silicon body that occurs before the peak transconductance is reached, in the saturation region of operation. The proposed coupling relationship effectively captures this behavior, ensuring symmetry of the overall model around
=
0 V and correct harmonic characteristics in linear and saturation regions, which are critical for RF IC design. An enhanced mobility model with improved body bias dependency has also been proposed that helps in the accurate validation of transconductance. The model is validated with state-of-the-art industry hardware data from GlobalFoundries. The model has been integrated into our new industry standard symmetric BSIM-SOI compact model framework.
The article deals with the complexity of the workflow used when integrated circuits are implemented using 2D electronic design automation (EDA) tools and adapting the workflow for 3D integrated circuits. If some issues are not identified promptly in the workflow, the working time to produce an integrated circuit is increased. By analyzing and refining workflow, identifying bottlenecks and early problems in a design, the optimization process will ensure an error-minimized trajectory from synthesis to final design prepared for manufacturing. Considering all the details at every stage of the working flow will help the backend designer to solve problems faster and save time. It was created detailed scripts for automatization of the process at every stage including floorplan, power plan, placement, clock tree synthesis, routing and all physical and logical analysis. The workflow was optimized using loops at all levels, extracting important information at every level and improving the process of working. Moreover, optimization techniques contribute significantly to precision and quality in design implementation. This working flow can be used to implement 3D integrated circuits with automated 2D tools from Synopsis.
The parallel and distributed programming is widely used in cloud computing. This is due to factors such as the popularization of multicore and heterogeneous CPU, which allow significant performance gains over sequential processing. ACM and IEEE recommend to teach the parallel and distributed programming and also provide details on how this topic should be studied in computing courses. However, the teaching of parallel programming is not trivial and differs in various undergraduate courses throughout countries. The differences include teaching approaches, theoretical and practical classes, instructional materials, embedded topics, number of hours, required and elective topics, prerequisites, among others. This article presents how the main institutions of higher education in the world approach the teaching of parallel programming, with the purpose of evaluating its adherence to the syllabus proposed by ACM and IEEE. The universities considered in this study were chosen according to a specific ranking and geographically separated by continent. After that, we compared with the ACM and IEEE-Computer Society reference curricula, highlighting the main differences. Our results show that there are still significantly differences regarding teaching HPC, mainly in relation to syllabus and topics covered, and that is hard to find available documents that show clearly how such subjects are conducted.
Wet etching of Silicon nitride (Si3N4) by phosphoric acid (H3PO4) is one of the key steps in the semiconductor fabrication process, especially for three‐dimensional integrated circuits (ICs). Unfortunately, few systematic studies of phosphoric acid etching of Silicon nitride are available. Summarizing how various factors affect etching and determining the reaction mechanism behind the etching process will help further optimize the etching process. In this work, how the boiling point of hydrous phosphoric acid solutions depends on phosphoric acid concentration is firstly investigated. Next, the etching of over 100 samples of Silicon nitride by H3PO4 at different concentrations and temperatures is systematically studied. The results show that the etching rate increases nearly linearly in both temperature and H3PO4 concentration, while temperature play more important role as compared to concentration. For each concentration, the reaction rate is maximal at the boiling point of the hydrous H3PO4 solution. Moreover, the etching rate of 85 wt % phosphoric acid is analyzed using the Arrhenius equation, yielding an apparent activation energy Ea=57.28 KJ/mol. Finally, a mechanism of Silicon nitride etching in phosphoric acid is proposed which explains the prior studies well. This work contributes to precisely control semiconductor processing for three‐dimensional ICs.
The copper foil can be well-bonded to alumina substrate at temperatures above the Cu–O eutectic temperature by the direct copper bonding technique. During the bonding process, voids and defects are easily formed at the Cu/Al2O3 interface, giving rise to reliability issues. This study explored the effects of different oxygen content in the form of the thickness of the cupric oxide layer on copper foils and the thickness of the electroless-plated nickel on alumina substrates on the void content of the direct copper-`bonded substrate. Research findings indicated that insufficient oxygen in the copper foil hindered the complete bonding of the Cu/Al2O3 interface due to an inadequate eutectic liquid phase. A successful bonding occurred between the copper foil pre-oxidized at 800 °C and the alumina substrate after 30 s of electroless nickel-plating (with a nickel layer thickness of about 0.02 μm). During high-temperature bonding, the Ni layer reacted with oxygen to form NiO, which then reacted with the cuprous oxide on the copper foil surface, forming a Ni-doped CuAlO2 phase. This phase effectively consumed oxygen during the bonding process, reducing the occurrence of voids. However, as the nickel coating thickness increased, the copper foil could not be bonded well to the alumina substrate because the thicker Ni reduced the oxygen content, preventing the formation of the Cu–O eutectic liquid phase.
In the era of Industry 4.0, the complexity of semiconductor production is growing very fast, raising the possibility of unnoticed defective wafers and subsequent wasteful use of resources. One of the key advantages of Industry 4.0 is the accessibility to big data, which can be obtained from a number of sensors, including multiple sensor data and extensive data repositories. Recently, engineers have developed data fusion strategies for virtual metrology (VM) prediction models to effectively handle data from multiple sources. This research explores a novel approach for data-driven VM prediction model for multi-source data, namely multi-source ensemble method with random source selection. By utilizing the bagging principle for multi-source data and tree-based prediction paradigms, the proposed approach randomly selects subsets of data sources to construct each tree learner, thus reducing interdependence among the trees and minimizing the risk of overfitting, which can be a challenge faced by existing tree-based prediction models. To validate and illustrate the practical applicability of our proposed method, we use real-world data from the plasma etching process, aiming to provide potential benefits and effectiveness of our methodology.
This study proposes a new chemical sensor designed using a single gate heterostructure dopingless tunnel field effect transistor (SG-HS-DLT). Combining Si0.6Ge0.4 in the source and HfO2 as the gate dielectric improves the sensor’s drain current sensitivity. Many chemical analytes, including hexane (C6H14), methanol (CH3OH), isopropanol (Iso-C3H7OH), dichloromethane (CH2Cl2), and chloroform (CHCl3) have been considered during the investigation. The conducting polymer is used as the gate metal due to its compatibility with the electronic chemical sensor. Modifying the gate work function with exposure to chemical substances is employed to determine the sensitivity of the reported chemical sensor. The electrical performance of the sensor is examined using transfer characteristics, switching ratio, average SS, BTBT rate, threshold voltage, electron concentration, energy band, and potential. Correspondingly, the sensitivity investigation comprises drain current sensitivity (SDrain), current ratio sensitivity (SR), average SS sensitivity (SAvgSS), and threshold voltage sensitivity (SVT). Further, the sensitivity analysis is extended for various temperatures and mole fractions (x). The SG-HS-DLT chemical sensor displays a higher value of SDrain of 3.64 × 10⁵, SAvg.SS of 0.69444 for CHCl3 at room temperature. This article extensively uses the Silvaco TCAD simulation software to investigate the proposed chemical sensor.
In the post-Moore era, main performance gains of black-box optimizers are increasingly depending on parallelism, especially for large-scale optimization (LSO). Here we propose to parallelize the well-established covariance matrix adaptation evolution strategy (CMA-ES) and in particular its one latest LSO variant called limited-memory CMA-ES (LM-CMA). To achieve efficiency while approximating its powerful invariance property, we present a multilevel learning-based meta-framework for distributed LM-CMA. Owing to its hierarchically organized structure, Meta-ES is well-suited to implement our distributed meta-framework, wherein the outer-ES controls strategy parameters while all parallel inner-ESs run the serial LM-CMA with different settings. For the distribution mean update of the outerES, both the elitist and multi-recombination strategy are used in parallel to avoid stagnation and regression, respectively. To exploit spatiotemporal information, the global step-size adaptation combines Meta-ES with the parallel cumulative stepsize adaptation. After each isolation time, our meta-framework employs both the structure and parameter learning strategy to combine aligned evolution paths for CMA reconstruction. Experiments on a set of large-scale benchmarking functions with memory-intensive evaluations, arguably reflecting many data-driven optimization problems, validate the benefits (e.g., effectiveness w.r.t. solution quality, and adaptability w.r.t. secondorder learning) and costs of our meta-framework
The switching response in organic electrochemical transistors (OECT) is a basic effect in which a transient current occurs in response to a voltage perturbation. This phenomenon has an important impact on different aspects of the application of OECT, such as the equilibration times, the hysteresis dependence on scan rates, and the synaptic properties for neuromorphic applications. Here we establish a model that unites vertical ion diffusion and horizontal electronic transport for the analysis of the time‐dependent current response of OECTs. We use a combination of tools consisting of a physical analytical model; advanced 2D drift‐diffusion simulation; and the experimental measurement of a poly(3‐hexylthiophene) (P3HT) OECT. We show the reduction of the general model to simple time‐dependent equations for the average ionic/hole concentration inside the organic film, which produces a Bernards‐Malliaras conservation equation coupled with a diffusion equation. We provide a basic classification of the transient response to a voltage pulse, and the correspondent hysteresis effects of the transfer curves. The shape of transients is basically related to the main control phenomenon, either the vertical diffusion of ions during doping and dedoping, or the equilibration of electronic current along the channel length.
Computer vision applications involving digital forensic investigations widely use digital images as legal documentary proof. Ensuring the authenticity and reliability of digital images by locating potential tampering is a critical area of concern for forensic applications. Splicing is one of the most commonly used methods for image tampering in digital domains. This systematic literature review (SLR) is conducted using PRISMA guidelines to explore the opportunities and challenges in the image splicing detection and localization (ISDL) domain. A total of 99 empirical papers were selected for an in-depth review from four major databases: IEEE Explore, Science Direct, Springer, and Web of Science. Papers were selected based on specific inclusion and exclusion criteria, focusing solely on those addressing deep learning, machine learning, transfer learning, and quantum computing technologies. The survey was conducted by framing 8 research questions based on ISDL to identify potential answers to its implementation. The synthesis shows that 83.84% of the ISDL studies were based on generic applications, and 73.74% of the studies utilized machine learning models for classification. Furthermore, accuracy, F1-score, and sensitivity were the most preferred evaluation metrics used by 63.64%, 38.38%, and 36.36% of studies, respectively. For ISDL applications, 54.54% of the studies used CASIA TIDE v2.0, and 37.37% incorporated graphics processing units (GPU). This paper presents a thorough synthesis of existing studies in the ISDL domain while highlighting the importance of various emerging technologies in dealing with digital forensics. The outcomes are expected to be useful to industry experts, researchers, and policymakers to establish safe practices in computer vision applications.
Nanoelectronic Devices and Applications presents reviews on recent advances in nanoelectronic device design and new directions for their practical use. The volume includes 16 edited chapters that cover novel material systems, band engineering, modelling and simulations, fabrication and characterization techniques, and their emerging applications. The discussions presented in this book are based on current understandings on innovations and future trends, and references are provided for advanced scholars. Chapter 1 presents an overview of recent innovations and future prospects in III-nitride semiconductor technologies for RF, power, digital and quantum applications. Chapter 2 reports new trends in GaN-based optical devices for sensing and micro-display applications. Chapter 3 shows current interests in nanophosphors and their utilizations in improving device performance of InGaN nanowire light-emitting diodes (LEDs). Recent studies on the effect of potential profile on the carrier transport in AlGaAs based double quantum well structures and their applications are presented in Chapter 4. The recent progress in high-electron-mobility transistors (HEMTs) is presented through Chapters 5, 6, and 7. A comprehensive review on β-Ga2O3 emphasizing material properties, growth approaches, and its applications for next-generation high-power nanoelectronics; the effect of dielectric layers on the characteristics of AlN/β-Ga2O3 HEMTs are presented in Chapter 8 and 9 respectively. Chapters 10-14 summarize the recent studies in field-effect transistors (FETs) adopting different materials and structures. Chapter 15 presents current research in 2D Tungsten Diselenide (WSe2) with special focus on the material properties, device structures, applications, and challenges. Finally, Chapter 16 presents a systematic review of memristors, and memristive semiconductor devices. The book is intended as a primary resource for elective subjects in advanced electronics and computer engineering courses at university level. Researchers and industry professionals will also learn about emerging trends and state-of-the-art research in nanoelectronics.
Para-substituted benzenes, such as 1,4-benzene dithiol and 1,4-phenyl diisocyanide, have been observed to oligomerize on the Au(111) surface by incorporating gold adatoms extracted from the substrate. This work investigates if oligomerization occurs for an analogous but asymmetric linker, 4-isocyanophenyl disulfide (ICPD) on Au(111). This molecule is comprised of both disulfide and isocyanide terminal groups attached to the phenyl ring. The resulting surface structures formed on Au(111) following exposure to ICPD are studied using scanning tunneling microscopy (STM). 1,4-isocyanophenyl thiolate (ICPT), formed through scission of ICPD’s disulfide bond, was also found to oligomerize on the surface, and potential oligomer structures and binding geometries are proposed with the aid of density functional theory (DFT) calculations, along with simulated STM images of the resulting structures. It is observed in this work that ICPT forms oligomeric structures that cover large sections of the substrate and appear to create etch pits resulting from gold atom extraction. Numerous potential binding geometries are investigated based on the distances between substrate gold atom adsorption sites compared to the monomer length. Selected structural candidates were optimized using DFT and were used to generate simulated STM images using the Tersoff–Hamann method to compare with experiment. It has been shown previously that the isocyanide- and thiol-connected oligomers conduct electrons, suggesting the possibility that the asymmetric oligomers found here might form the basis for fabricating molecular diodes.
In this paper for the first time, we have studied various structures of nanosheet field-effect transistors (NSFET) and the effect of various devices and process parameters such as nanosheet width, length, interspacing, S/D doping, channel doping, random dopant fluctuations studied on these device structures. Comparative analysis has been done between JL-NSFET, GS-JL-NSFET, JL-SiGeNSFET and JL-GS-SiGeNSFET in terms of analog parameters. Nanosheet-based FETs are likely to be the successor of FinFET beyond the 5-nm node. NSFETs have better control over gate, variable sheet width and more current per device footprint which gives them the advantage of circuit design versatility. NSFET offers better gate control, better current and switching per device footprint. NSFETs are preferred over NWFETs due to better electrostatics, greater channel widths, decreased SCEs and increased device reliability.
Plasma etching is an essential semiconductor manufacturing technology required to enable the current microelectronics industry. Along with lithographic patterning, thin-film formation methods, and others, plasma etching has dynamically evolved to meet the exponentially growing demands of the microelectronics industry that enables modern society. At this time, plasma etching faces a period of unprecedented changes owing to numerous factors, including aggressive transition to three-dimensional (3D) device architectures, process precision approaching atomic-scale critical dimensions, introduction of new materials, fundamental silicon device limits, and parallel evolution of post-CMOS approaches. The vast growth of the microelectronics industry has emphasized its role in addressing major societal challenges, including questions on the sustainability of the associated energy use, semiconductor manufacturing related emissions of greenhouse gases, and others. The goal of this article is to help both define the challenges for plasma etching and point out effective plasma etching technology options that may play essential roles in defining microelectronics manufacturing in the future. The challenges are accompanied by significant new opportunities, including integrating experiments with various computational approaches such as machine learning/artificial intelligence and progress in computational approaches, including the realization of digital twins of physical etch chambers through hybrid/coupled models. These prospects can enable innovative solutions to problems that were not available during the past 50 years of plasma etch development in the microelectronics industry. To elaborate on these perspectives, the present article brings together the views of various experts on the different topics that will shape plasma etching for microelectronics manufacturing of the future.
We conducted a study on the frequency dependence analysis of soft error rates using the test circuit composed of scan flip-flops (FFs) and inverters. By irradiating the circuit with alpha particles while the clock was running, soft error rates were measured. During alpha-particle irradiation, soft errors caused by inverters were almost negligible. Soft errors caused by FFs decreases as the operating frequency increases. On the other hand, during Ar irradiation, soft error rate was nearly constant with varying frequency. This is because, the increase in soft errors caused by inverters was roughly equal to the decrease in soft errors caused by FFs unlike alpha-particle irradiation.
In this work, we studied the characteristics of Cu-Cu bonding with a ruthenium passivation layer at low temperatures. It is confirmed that the ruthenium passivation layer is effective in preventing the formation of native copper oxide, and diffusion of the copper into the ruthenium passivation layer occurred sufficiently at 200°C. The Cu samples with the ruthenium passivation layer were successfully bonded at 200°C. They exhibited excellent shear strength of 17.16 MPa, and the specific contact resistance of 1.78×10
-7
Ω·cm
2
at the bonding interface. With the results, we expect that along with improving the thermal budget of the bonding process, it will be able to contribute to improving the chip performance and reliability of heterogeneous integrated structures.
Boltzmann carrier statistics restrict the sub‐threshold swing (SS ≥ 60 mVdec–1) and, consequently, the supply voltage (≈ 1 V) of the thermionic transistor. This primary bottleneck results in rapidly increasing power consumption, heating, and associated reliability/scalability challenges as more devices are packed into a small footprint. Despite significant efforts from the device community, a suitable sub‐thermionic alternative is yet to emerge. In this work, an attempt is made to understand the physics of Schottky barrier FETs demonstrating SS < 60 mVdec–1, as evident in some experimental results. Employing the in‐house TCAD tool, the electrostatic potential in the device is accurately modeled with the sweeping gate bias. Next, the Tsu–Esaki model is used to compute the tunneling current. The analysis shows that the steep SS results from an abrupt change in the tunneling barrier profile, from a step‐like to a triangular‐like. However, in the ON regime, the drift component begins to dominate the transfer characteristics. Thus, the subtle interplay between the drift and tunneling components of transport leads to SS < 60 mVdec–1 in OFF‐state with improved Ion in ON‐state. Finally, using the calibrated model, the performance metrics of an all‐2D material‐based CMOS inverter operating at a low VDD ≈ 0.6 V are projected.
In this study, we compare the implementation of the rectified linear (ReLU) activation function using transition metal dichalcogenide field-effect transistors (TMDFETs) and metal-oxide-semiconductor FETs (MOSFETs). Five TMDs - MoS 2, MoSe 2, MoTe 2, WS 2, WSe 2 along with three variants (low-power, high-performance, and multi-gate) of the MOSFETs are simulated. Three ReLU circuits utilizing these FETs are employed for the comparison. The power consumption, speed, and accuracy of the ReLU implementation are measured and compared for each circuit and each FET. Our simulation results show that the MOSFETs consume much less power than the TMDFETs and deliver more accurate ReLU functionality. However, the TMDFETs are much faster than the MOSFETs. Among the TMDFETs, the WS 2 FET stands out, as it has higher accuracy, consumes the least power and its power consumption is comparable to the MOSFETs. Additionally, WS 2 is faster compared to MOSFETs, resulting in a trade-off between power efficiency and speed. This makes WS 2 an attractive option for implementing the ReLU activation function.
The number of photonic components integrated into the same circuit is approaching one million, but so far, this has been without the large-scale integration of active components: lasers, amplifiers, and high-speed modulators. Emerging applications in communication, sensing, and computing sectors will benefit from the functionality gained with high-density active–passive integration. Indium phosphide offers the richest possible combinations of active components, but in the past decade, their pace of integration scaling has not kept up with passive components realized in silicon. In this work, we offer a perspective for functional scaling of photonic integrated circuits with actives and passives on InP platforms, in the axes of component miniaturization, areal optimization, and wafer size scaling.
Electronic health record (EHR) systems have developed over time in parallel with general advancements in mainstream technology. As artificially intelligent (AI) systems rapidly impact multiple societal sectors, it has become apparent that medicine is not immune from the influences of this powerful technology. Particularly appealing is how AI may aid in improving healthcare efficiency with note-writing automation. This literature review explores the current state of EHR technologies in healthcare, specifically focusing on possibilities for addressing EHR challenges through the automation of dictation and note-writing processes with AI integration. This review offers a broad understanding of existing capabilities and potential advancements, emphasizing innovations such as voice-to-text dictation, wearable devices, and AI-assisted procedure note dictation. The primary objective is to provide researchers with valuable insights, enabling them to generate new technologies and advancements within the healthcare landscape. By exploring the benefits, challenges, and future of AI integration, this review encourages the development of innovative solutions, with the goal of enhancing patient care and healthcare delivery efficiency.
Wafer bonding is a key process in heterogeneous photonic integration and benzocyclobutene (BCB) is widely used for adhesive wafer-to-wafer bonding when it comes to handling complex topography on both wafers. However, until now a major drawback of bonding with BCB was the high thermal resistance of lasers due to the low thermal conductivity of BCB. We demonstrate, that by optimizing the membrane device topography and introducing the BCB reflow step into the process flow it is possible to achieve full planarization of 1 m topography at the wafer scale while ensuring only 250 nm of BCB between the laser p-contact and the substrate. We show experimentally, that the thermal impedance of 500 m long DFB laser was reduced from 585 K/W to 271 K/W, and there is room to reduce it further to less than 150 K/W by adjusting the BCB thickness and changing the substrate to SiC.
Motives: The solutions for designing spatial development methods in planning documents are presented as 2D graphics with supplementary descriptions. Due to the lack of specialist knowledge and insufficient spatial imagination, some readers may be unable to understand the graphic and descriptive content of such documents. The above can lead to the construction of objects that disrupt spatial order without violating the law. This problem can be solved by applying augmented reality (AR) in spatial planning. This paper presents the capabilities of a method for visualizing different spatial development variants on the example of buildings. A model of a building plot and the surrounding area, covered by a local spatial development plan, was developed. Aim: The aim of this study was to determine the applicability of the AR technology for identifying low-precision areas in the plan and its potential impact on the method of land development, with a resulting deterioration in spatial order. Results: The use of the AR technology enables analyses and assessments of planned development in the context of spatial order and its integration with the existing elements. Visualizations presented with the AR technology show that different interpretations of the local zoning plan generate spatial chaos. The utility of 3D visualization for an average reader was also presented. The AR technology can be used at the stage of preparing planning documents (community participation, adopting the plan), adopting by-laws (councilors), and enforcing these regulations (investors' decisions).
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