VLSI design and analysis of low power 6T SRAM cell using cadence tool

Conference Paper · December 2008with587 Reads
DOI: 10.1109/SMELEC.2008.4770289 · Source: IEEE Xplore
Conference: Semiconductor Electronics, 2008. ICSE 2008. IEEE International Conference on
CMOS SRAM cell is very less power consuming and have less read and write time. Higher cell ratios can decrease the read and write time and improve stability. PMOS transistor with less width reduces the power consumption. This paper implements 6T SRAM cell with reduced read and write time, area and power consumption. It has been noticed often that increased memory capacity increases the bit-line parasitic capacitance which in turn slows down voltage sensing and make bit-line voltage swings energy expensive. This result in slower and more energy hungry memories.. In this paper Two SRAM cell is being designed for 4 Kb of memory core with supply voltage 1.8 V. A technique of global bit line is used for reducing the power consumption and increasing the memory capacity.
    • "It can be seen that increased memory capacity increases the bit line parasitic capacitance which in turn slows down voltage sensing and make bit-line voltage swings energy expensive. This result shows the slower and more energy hungry memories [3]. Reverse short channel effect is utilized in SRAM cell design which improves cell write margin and read performance without using additional circuits. "
    [Show abstract] [Hide abstract] ABSTRACT: Power Stringent Static Random Access Memory (SRAM) design is very much essential in embedded systems such as biomedical implants, automotive electronics and energy harvesting devices in which battery life, input power and execution delay are of main concern. With reduced supply voltage, SRAM cell design will go through severe stability issues. In this paper, we present a highly stable average nT SRAM cell for ultra-low power in 125nm technology. The distinct difference between the proposed technique and other conventional methods is about the data independent leakage in the read bit line which is achieved by newly introduced block mask transistors. An average 6.5T SRAM and average 8T SRAM are designed and compared with 6T SRAM, 8T SRAM, 9T SRAM, 10T SRAM and 14T SRAM cells. The result indicates that there is an appreciable decrease in power consumption and delay.
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  • [Show abstract] [Hide abstract] ABSTRACT: In this paper a new 5T SRAM cell is proposed with fast performance, high density and low power consumption. The proposed CMOS SRAM cell consumes less power and has less read and write time. It is capable of storing the bits effectively. The novel cell size is 24.37% smaller than the conventional six-transistor SRAM cell using same design rules without any performance degradation. Simulation results show that there is substantial improvement in performance of the proposed cell as regards performance parameters like delay, power consumption and leakage current. The novel configuration has been analyzed using cadence virtuoso tool in 45nm technology node.
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  • [Show abstract] [Hide abstract] ABSTRACT: Leakage power is a major issue for short channel devices. As the technology is shrinking (i.e., 180nm, 90nm, 45nm. etc.) the leakage current is increasing very fast. So, several methods and techniques have been proposed for leakage reduction in CMOS digital integrated circuits. Leakage power dissipation has become a sizable proportion of the total power dissipation in integrated circuit. This paper demonstrates the ideas of 6T, 8T and 10T models with sleep transistors. This proposed SRAM cells give the advantages over basic 6T, 8T and 10T transistor models. The SRAM cell with sleep transistor shows better leakage reduction approach than stack approaches. Here in this paper Analog environment virtuoso (cadence) simulator is used for analysis of the power associated with CMOS SRAM cell for 180nm technology.
    Article · Nov 2014 · Leonardo Electronic Journal of Practices and Technologies
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