Conference Paper

VLSI design and analysis of low power 6T SRAM cell using cadence tool

Dept. of ECE, Maulana Azad Nat. Inst. of Technol., Bhopal
DOI: 10.1109/SMELEC.2008.4770289 Conference: Semiconductor Electronics, 2008. ICSE 2008. IEEE International Conference on
Source: IEEE Xplore


CMOS SRAM cell is very less power consuming and have less read and write time. Higher cell ratios can decrease the read and write time and improve stability. PMOS transistor with less width reduces the power consumption. This paper implements 6T SRAM cell with reduced read and write time, area and power consumption. It has been noticed often that increased memory capacity increases the bit-line parasitic capacitance which in turn slows down voltage sensing and make bit-line voltage swings energy expensive. This result in slower and more energy hungry memories.. In this paper Two SRAM cell is being designed for 4 Kb of memory core with supply voltage 1.8 V. A technique of global bit line is used for reducing the power consumption and increasing the memory capacity.

501 Reads
  • [Show abstract] [Hide abstract]
    ABSTRACT: In this paper a new 5T SRAM cell is proposed with fast performance, high density and low power consumption. The proposed CMOS SRAM cell consumes less power and has less read and write time. It is capable of storing the bits effectively. The novel cell size is 24.37% smaller than the conventional six-transistor SRAM cell using same design rules without any performance degradation. Simulation results show that there is substantial improvement in performance of the proposed cell as regards performance parameters like delay, power consumption and leakage current. The novel configuration has been analyzed using cadence virtuoso tool in 45nm technology node.
    No preview · Conference Paper · Mar 2014
  • [Show abstract] [Hide abstract]
    ABSTRACT: SRAM is a main part of cache, therefore its power consumption reduction has always been researched. The present work aims to reduce leakage power without affecting the logic state of SRAM cell. For achieving this subthreshold operation is carried out. Furthermore two different techniques are analyzed for the same namely forced stack transistor technique and sleep transistor technique. It is seen from the analysis that sleep transistor technique shows less average power dissipation compared to others whereas forced stack transistor technique gives minimum average delay compared to others. A convincing power reduction is achieved in a SRAM cell with minimum critical path delay using sleep transistor technique. Simulations are carried out using TSPICE for 90nm, 45nm and 32nm CMOS technology nodes. For subthreshold operation the supply voltage 0.35V is used.
    No preview · Article · Apr 2015
  • Source
    [Show abstract] [Hide abstract]
    ABSTRACT: The paper presents a novel 8T SRAM cell with access pass gates replaced with modified PMOS pass transistor logic. In comparison to 6T SRAM cell, the proposed cell achieves 3.5x higher read SNM and 2.4x higher write SNM with 16.6% improved SINM (static current noise margin) distribution at the expense of 7x lower WTI (write trip current) at 0.4 V power supply voltage, while maintaining similar stability in hold mode. The proposed 8T SRAM cell shows improvements in terms of 7.735x narrower spread in average standby power, 2.61x less in average TWA (write access time), and 1.07x less in average TRA (read access time) at supply voltage varying from 0.3 V to 0.5 V as compared to 6T SRAM equivalent at 45 nm technology node. Thus, comparative analysis shows that the proposed design has a significant improvement, thereby achieving high cell stability at 45 nm technology node.
    Full-text · Article · Sep 2015 · International Journal of Reconfigurable Computing