Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques

ArticleinCircuits and Systems II: Express Briefs, IEEE Transactions on 56(1):41 - 45 · January 2009with27 Reads
DOI: 10.1109/TCSII.2008.2010163 · Source: IEEE Xplore
A family of tunable MOS resistors based on quasi-floating-gate (QFG) transistors biased in the triode region is analyzed in this paper. From the study results, a new device that outperforms previous implementations, is presented. By means of a capacitive divider, the ac component of the drain-to-source voltage scaled with a factor alpha les 1 is added to the gate-to-source voltage leading to a cancellation of the nonlinear terms. The effect of alpha on resistor linearity is analytically studied. Simulation results are also provided for different technologies. Finally, a complete transconductor has been built which preserves the linearity of the MOS resistor. Three versions of the transconductor have been fabricated for different values of alpha (alpha = 0, 0.5, and 1) in a 0.5 mum CMOS technology with plusmn1.65-V supply voltage. Experimental results show (for alpha = 1 ) a THD of - 57 dB (HD2=-70 dB) at 1 MHz for 2-V peak-to-peak differential input signal with a nominal ac-transconductance of 200 muA/V and a power consumption of 3.2 mW.
    • "Additionally, it avoids the effect of parasitic resistive dividers formed by the combination of resistors r ds1 , r ds2 and r ds3 and the distributed leakage resistance of the respective well-substrate junction [5], [6]. Regrettably, r ds1 , r ds2 and r ds3 present significant distortion motivated by V DS drops, body effect and mobility degradation [5]. A successful linearization of R 1 , R 2a and R 2b can be obtained by employing the so called " common-mode " linearization technique [4], performed by transistor M p4 and capacitors C a . "
    Full-text · Conference Paper · Nov 2015 · International Journal of Circuit Theory and Applications
    • "Some recent works try to achieve G m -C filters comparable in terms of linearity to active- RC topologies, using passive resistors to perform the V-I conversion [6, 7], mixed source degeneration structures formed by resistors and triode transistors [8, 9], or cross-coupled MOS transistors [10]. Furthermore, techniques based on quasi-FGMOS (QFGMOS) transistors have been proposed for linearizing triode transistors in source degeneration structures [11]. Concerning low-voltage low-power transconductor design, the use of the substrate as active terminal [12, 13] or the use of FGMOS transistors for reducing the threshold voltage and compressing the signal swing to increase the operation range141516 are worth mentioning, to name a few techniques. "
    [Show abstract] [Hide abstract] ABSTRACT: A novel Gm-C filter design technique is presented. It is based on floating-gate metal oxide semiconductor (FGMOS) transistors and consists in a topological rearrangement of conventional fully differential Gm-C structures without modifying the employed transconductors at transistor level. The proposed method allows decreasing the number of active elements (transconductors) of the filter. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. The features of the proposed technique are fully exploited in all-pole Gm-C filter design, specially implementing unity gain Butterworth transfer functions. Thus, two low-power second-order Butterworth Gm-C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method. Measurement results for a test chip prototype in a 0.5-µm standard complementary MOS process are presented, confirming the advantages of the proposed FGMOS design technique. Copyright © 2014 John Wiley & Sons, Ltd.
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    • "Several FG based applications can be found out of which few are related to design of multiplier, transconductor, filter, I-V converter, CM with wide dynamic range and enhanced bandwidth and many other concerned to low voltage applications such as CM with enhanced bandwidth [7], CM with enhanced characteristics [8]. Taking advantage of capacitor divider property, some QFG based transistors were used for design of very linear programmable CMOS OTA [9] which further used to implement tunable MOS resistors [10] and also GM-C filter [11]. Other recent published articles are based on current conveyor [12], CM having low input compliance voltage [13]. "
    [Show abstract] [Hide abstract] ABSTRACT: This paper presents a detail on various techniques to realize low voltage low power circuit. The techniques discussed are conventional gate-driven (GD), floating gate (FG), quasi-floating gate (QFG), bulk-driven (BD), and BD-QFG. The comparative analysis results in best performance achieved by BD-QFG approach. As BD circuits are well known approach for low power design, the combined effect QFG in bulk driven circuit results in enhanced performance. The complete analysis has been carried out in industry specific node UMC 0.18 micron technology with the help of HSpice simulator.
    Full-text · Article · Jun 2015
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