Conference Paper

The time-triggered System-on-a-Chip architecture

Real-Time Syst. Group, Vienna Univ. of Technol., Vienna
DOI: 10.1109/ISIE.2008.4677135 Conference: Industrial Electronics, 2008. ISIE 2008. IEEE International Symposium on
Source: IEEE Xplore


It is the objective of the presented System-on-a-Chip (SoC) architecture to provide a predictable integrated execution environment for the component-based design of many different types of embedded applications (e.g., automotive, avionics, consumer electronics). At the core of this architecture is a time-triggered network-on-a-chip for the predictable interconnection of heterogeneous components. A component can be a self-contained computer, including system and application software, an FPGA, or a custom hardware unit. By providing a single uniform interface to all types of components for the exchange of messages, the architecture supports the component-based design of large applications and enables the massive reuse of components. The time-triggered network-on-a-chip offers inherent fault isolation to facilitate the seamless integration of independently developed components, possibly with different criticality levels. Furthermore, mechanisms for integrated resource management support dynamically changing resource requirements (e.g., different operational modes of an application), fault-tolerance, a power-aware system behavior, and the implementation of fault-handling by reconfiguration.

Full-text preview

Available from:
  • Source
    • "As a technical solution, the GENESYS project promoted an SoC which uses a time–triggered NoC to interconnect heterogeneous IP cores. The technological background was researched in the TTSoC project [15] [16]. After the completion of GENESYS, the INDEXYS project [17] took over the development by providing a proof–of–concept implementation. "
    [Show abstract] [Hide abstract]
    ABSTRACT: The European ARTEMIS ACROSS project aims to overcome the limitations of existing Multi-Processor Systems-on-a-Chip (MPSoC) architectures with respect to safety-critical applications. MPSoCs have a tremendous potential in the domain of embedded systems considering their enormous computational capacity and energy efficiency. However, the currently existing MPSoC architectures have significant limitations with respect to safety-critical applications. These limitations include difficulties in the certification process due to the high complexity of MPSoCs, the lacking temporal determinism and problems related to error propagation between subsystems. These limitations become even more severe, when subsystems of different criticality levels have to be integrated on the same computational platform. Examples of such mixed-criticality integration are found in the avionics and automotive industry with their desire to integrate safety-critical, mission critical and non-critical subsystems on the same platform in order to minimize size, weight, power and cost. The main objective of ACROSS is to develop a new generation of multi-core processors designed specially for safety-critical embedded systems; the ACROSS MPSoC. In this paper we will show how the ACROSS MPSoC overcomes the limitations of existing MPSoC architectures in order to make the multi-core technology available to the safety-critical domain.
    Full-text · Conference Paper · Sep 2012
  • Source
    • "III. TIME-TRIGGERED MULTI-PROCESSOR SYSTEM-ON-A-CHIP WITH FAULT-CONTAINMENT The Time-Triggered System-on-a-Chip (TTSoC) [13] encompasses a set of components (cf. Figure 1) each of which is a self-contained hardware/software subsystem. The TTSoC permits a wide range of implementation choices for components , such as a dedicated hardware realization or a component implementation as a general purpose CPU with an operating system, middleware and application software. "
    [Show abstract] [Hide abstract]
    ABSTRACT: Fault containment between components is a significant property in embedded real-time systems in order to improve robustness, attain clear integration responsibilities and enable modular certification. This paper presents fault containment mechanisms, which are based on the time-triggered Network-on-a-Chip (NoC) of a reconfigurable MPSoC. Each component accesses this NoC via a communication interface that acts as a guardian of the component behavior in the time and value domain. The knowledge about the permitted behavior of a component is written into the communication interfaces by a trusted resource manager. We perform an evaluation of these fault containment capabilities using fault injection experiments. The experiments provide evidence that a faulty component cannot affect the timing or integrity of messages exchanged by other components.
    Preview · Article · Jun 2011
  • Source
    • "Although the proposed CAN router could be used in redundant multiple star architectures (e.g., similar to solutions for other communication protocols [9]), this approach would not be compatible with existing CAN nodes and involve significant cost. However, in order to support the assumption of the correct operation of the CAN router, we have implemented the router using a fault-tolerant MPSoC architecture [12] as described in Section IV. The encapsulation mechanisms of this architecture [11] ensure that a local failure of the subsystem associated with a CAN port in the router cannot affect the correct operation of subsystems associated with other CAN ports. "
    [Show abstract] [Hide abstract]
    ABSTRACT: Controller Area Network (CAN) provides an inexpensive and robust network technology in many application domains. However, the use of CAN is constrained by limitations with respect to fault isolation, bandwidth, wire length, namespaces and diagnosis. This paper presents a solution to overcome these limitations by replacing the CAN bus with a star topology. We introduce a CAN router that detects and isolates node failures in the value and time domain. The CAN router ensures that minimum message interarrival times are satisfied and reserves CAN identifiers for individual CAN nodes. In addition, the CAN router exploits knowledge about communication relationships for a more efficient use of communication bandwidth through multicast messaging. An implementation of the CAN router based on a Multi-Processor System-on-a-Chip (MPSoC) shows the feasibility of the proposed solution.
    Preview · Conference Paper · Aug 2010
Show more