Design-for-testability techniques for motion estimation computing arrays

Conference Paper · June 2008with25 Reads
DOI: 10.1109/ICCCAS.2008.4657979 · Source: IEEE Xplore
Conference: Communications, Circuits and Systems, 2008. ICCCAS 2008. International Conference on


    In this paper, a testable 2-D motion estimation (TME) design at the bit level (TME<sub>bit</sub>) based on the C-testability conditions are proposed. In order to meet the testability conditions, the bit-level cell functions are made bijective. Our C-testability conditions guarantee about 100% fault coverage for single cell fault model with a constant number of test patterns. The number of test patterns is 128. To verify the proposed technique, an experimental chip is implemented with TSMC 0.18 mum technology. According to experimental results, the gate count of the design is about 159 K and the design can operate at the frequency up to 100 MHz. The hardware overhead used to make it C-testable is about 7%.