With the advent of chip multiprocessors (CMPs) in mainstream systems, the on-chip network that connects different processing cores becomes a critical part of the design. There has been significant work in the recent past on designing these networks for efficiency and scalability. However, most network design evaluations use a stand-alone network simulator which fails to capture the system-level implications of the design. New design innovations, which might yield promising results when evaluated using such stand-alone models, may not look that attractive when evaluated in a full-system simulation framework. In this work, we present GARNET, a detailed network model incorporated inside a full-system simulator which enables system-level performance and power modeling of network-level techniques. GARNET also facilitates accurate evaluation of techniques that simultaneously leverage the memory hierarchy as well as the interconnection network. We also discuss express virtual channels, a novel flow control technique which improves network energy/delay by creating virtual lanes in the network along which packets can bypass intermediate routers.
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"Some simulator, such as ASIM , provides a unique solution, but only implements a unique interconnection network. Others combine the two first approaches, such as Sicosys+RSIM or GEMS+GARNET . They offer an interface between these two simulators and can perform the simulation of the entire platform with communication accuracy. "
[Show abstract][Hide abstract]ABSTRACT: The need for computing power drastically increases and one solution is to use MPSoC. These MPSoCs become complex with the increase of the number of cores. Thus, designers use simulators to explore the whole platform parameters in order to define the best architecture. These simulators must be fast and accurate whatever is the architecture complexity. This paper introduces a new approximate-timed TLM approach to provide a speed up of at least x100 on the simulation time in comparison with a timed TLM approach. This new communication method allows fast and accurate hardware parameter exploration of MPSoC with a standard SystemC protocol. The lack of accuracy in networks-on-chip can affect the execution order, but the opposite slows down simulation and cannot support MPSoC exploration. For this reason, this paper focuses on networks-on-chip to demonstrate the benefits of our approximate-timed TLM approach.
"Garnet  is a network-on-chip performance simulator which is compatible with the GEMS  multiprocessor framework with Simics . It can be interfaced with the Orion  network-on-chip power modeler when necessary. "
[Show abstract][Hide abstract]ABSTRACT: This paper describes NoCBench, a benchmarking platform for evaluating the performance of Network-on-chip enabled Systems-on-chip. NoCBench includes an initial set of standardized processing cores, NoC components, and application benchmarks for system-level design exploration and analysis. It uses the NoCSim network on-chip simulator as the core simulation engine to execute these models and applications. We also present a simple case study to demonstrate the capability of the simulation environment.
[Show abstract][Hide abstract]ABSTRACT: The huge design space of Network-on-Chip raise the need of simulators for NoC to efficiently evaluate the performance and select the optimal architecture. This paper presents a review of research on NoC simulators, differentiates the current approaches into three categories: regular network simulators, dedicated NoC simulators, and full-system simulators. We compares the current NoC simulators according to topologies, routing and switching algorithms, traffic models, and discuss the open issues and developing trends in this field.