Conference Paper

Efficient construction and implementation of short LDPC codes for wireless sensor networks

Dept. of Microelectron. Eng., Univ. Coll. Cork, Cork
DOI: 10.1109/ECCTD.2007.4529693 Conference: Circuit Theory and Design, 2007. ECCTD 2007. 18th European Conference on
Source: IEEE Xplore


Wireless sensor networks gained a lot of attention in recent years due to their widespread applications. Reliability of data communication and power saving are paramount for applications which use wireless sensor network technology. We propose two classes of short quasi-cyclic LDPC codes suitable for implementation on a resource constrained system. The codes we propose are easy to encode and their decoding performance compares well with random LDPC codes with the same parameters. We implement our codes on a 25 mm mote platform provided by Tyndall and compare them with Viterbi coding schemes.

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    • "Therefore an LDPC decoding algorithm whose BER performance can be traded off with respect to its energy efficiency is highly desirable. For example, in [3], [4] both BER and energy efficiency have been simultaneously considered, however, the typical approach has been to fix one metric while optimizing the other. In our previous work, we had reported a margin propagation based LDPC decoding algorithm [5], [6] and we demonstrated that MP decoder can efficiently trade off BER with energy efficiency through a choice of a hyper-parameter. "
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    ABSTRACT: One of the key factors underlying the popularity of low-density parity-check (LDPC) codes is its iterative decoding algorithm which is amenable to efficient analog and digital implementation. However, different applications of LDPC codes (e.g. wireless sensor networks) impose different sets of constraints which include speed, bit error rates (BER) and energy efficiency. Our previous work reported an algorithmic framework for designing margin propagation (MP) based LDPC decoders where the BER performance can be traded off with its energy efficiency. In this paper we present an analog current-mode implementation of an MP-based (32;8) LDPC decoder. The implementation uses only addition, subtraction and threshold operations and hence is independent of transistor biasing and robust to variations in environmental conditions (e.g. temperature). Measured results from prototypes fabricated in a 0.5m CMOS process verify the functionality of a (32;8) LDPC decoder and demonstrate superior BER performance compared to the state-of-the-art analog min- sum decoder at SNR greater than 3.5 dB. Index Terms—error-correction circuits, low-density parity- check (LDPC) decoder, margin propagation (MP), analog de- coders, current-mode circuits
    Full-text · Conference Paper · May 2011
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    ABSTRACT: A wireless sensor network (WSN) usually consists of a large number of battery-powered low-cost sensors with limited data collection and processing capacity. In order to prolong the lifetime of the WSN with a target error performance, a novel clustered distributed coding framework, referred to as distributed multiple-sensor cooperative turbo coding (DMSCTC), is developed for a large-scale WSN with sensor grouped in cooperative cluster. In the proposed DMSCTC scheme, a simple forward error correction is employed at each sensor and a simple multi-sensor joint coding is adopted at the cluster head, while complicated joint iterative decoding is implemented only at the data collector. The proposed DMSCTC scheme achieves extra distributed coding gain and cooperative spatial diversity without introducing extra complexity burden on the sensors by transferring the complicated joint decoding process to the data collector. With the proposed scheme, the WSN can achieve the target error performance with less power consumption, thus prolonging its lifetime. The error performance and energy efficiency of the proposed DMSCTC scheme are analyzed, and followed by Monte Carlo simulations. Both analytical and simulation results show that the DMSCTC can substantially improve the energy efficiency of the clustered WSN.
    No preview · Article · Nov 2013 · The Journal of Supercomputing