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IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS1
A Single-Waveguide In-Phase Power-Combined
Frequency Doubler at 190 GHz
José V. Siles, Member, IEEE, Alain Maestrini, Member, IEEE, Byron Alderman, Steven Davies, Hui Wang,
Jeanne Treuttel, Eric Leclerc, Tapani Närhi, Member, IEEE, and Christophe Goldstein
Abstract—This work represents the first demonstration of
in-phase power-combined frequency multipliers above 100 GHz
based on a dual-chip single-waveguide topology, which consists of
two integrated circuits symmetrically placed along the ?-plane
of a single transmission waveguide. This strategy increases by
a factor of 2 the maximum sustainable input power with re-
gard to traditional waveguide multipliers. A biasless 190 GHz
Schottky doubler based on this novel concept has been designed
and tested with a 6–10% conversion efficiency measured across a
177–202 GHz band when driven with a 50–100 mW input power
at 300 K.
Index Terms—Frequency multiplier, local oscillator, planar
Schottky diode, power-combining, submillimeter wavelengths.
preferred devices to up-convert the signal from the available
100–150 mW solid-state sources at W-band up to terahertz fre-
quencies , . The conversion efficiency of current Schottky
multipliers at 300 K ranges from
(triplers) @ 200 GHz to
@ 1.9 THz (1–3 output power) –. Other devices
such as Heterostructure Barrier Varactors (HBV) are suited
for odd-order multipliers and have reached 11% efficiency at
250 GHz . The recent progress in power-combined MMIC
amplifiers based on GaN transistors, providing up to 5 W at
W-band , makes it possible now to develop space-qualified
OR the last two decades, GaAs Schottky diode based
multiplied local oscillator (LO) sources have been the
@ 900 GHz and
Manuscript received October 22, 2010; revised January 04, 2011; accepted
March15, 2011.Thisworkwassupportedbythe EuropeanSpaceAgency ESA/
ESTEC under contract ITT AO/1-5084/06/NL/GL and by the Centre National
d’Etudes Spatiales, France.
J. V. Siles was with the Observatoire de Paris, LERMA, Paris 75014, France
A. Maestrini is with the Université Pierre et Marie Curie-Paris 6, Paris,
France, and also with the Observatoire de Paris, LERMA, Paris, France (e-mail:
B. Alderman and H. Wang are with the Space Science and Technology
Department, Rutherford Appleton Laboratory, Oxfordshire OX11 0QX, U.K.
S. Davies is with the Department of Physics, University of Bath, Bath BA2
7AY, U.K. (e-mail: firstname.lastname@example.org).
J. Treuttel is with the Observatoire de Paris, LERMA, Paris 75014, France
E. Leclerc is with United Monolithic Semiconductors (UMS), Orsay 91401,
France. (e-mail: email@example.com).
T. Närhi is with the ESTEC, European Space Agency, Noordwijk 2201AZ,
The Netherlands. (e-mail: firstname.lastname@example.org).
C. Goldstein is with the Centre National d’Etudes Spatiales, Toulouse 31401,
France. (e-mail: email@example.com).
Color versions of one or more of the figures in this letter are available online
Digital Object Identifier 10.1109/LMWC.2011.2134080
Fig. 1. Dual-chip single-waveguide power-combined scheme for multipliers.
designs to higher input powers, by increasing either the device
area or the number of diodes within the chip, is not possible due
to the circuit size limit imposed by the height of the transmis-
lutionsare necessary. Theuseof wide bandgap semiconduc-
tors such as GaN for the first multiplication stages may increase
the power-handling capabilities of Schottky diodes almost an
order of magnitude with similar anode areas . The number
of diodes can also be augmented by a factor of 2 by power
combining identical multipliers using compact Y-junctions or
hybrid couplers without affecting the efficiency with regard to
single-chip multipliers , . Moreover, quasi-optical power
combining has been successfully employed to combine the out-
puts of HBV arrays . Lastly, substrates with high-thermal
conductivity such as diamond can greatly reduce the multiplier
In this context, the topology shown in Fig. 1 represents a
further step in power-combined multipliers by adding an extra
symmetry plane to the circuit that allows twice the number of
diodes to be included. It features two MMIC chips symmetri-
cally placed along the
-plane within a unique transmission
waveguide (dual-chip single-waveguide scheme). This strategy
could double the power-handling capabilities of multipliers
without the necessity of duplicating the input and output
matching networks, unlike in , . In this work, a broadband
190 GHz doubler has been successfully designed and tested
using the standard BES Schottky diode process of UMS. Since
the diodes provided by UMS were not optimized for multiplier
operation, the final goal has not been to achieve state-of-the-art
efficiency but to prove the viability of the concept. The work
herein shows an excellent agreement between theory and
measurements and represents the first demonstration above
1531-1309/$26.00 © 2011 IEEE
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2 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS
Fig. 2. Quasi-TEM modes along the ?-plane of the rectangular waveguide: (a)
Perfect Electric Conductor plane of symmetry and (b) Perfect Magnetic Con-
ductor plane of symmetry. At ?-probes, field lines of the exciting ??
lines are at the OYZ cross-section indicated in Fig. 1.
100 GHz of this novel dual-chip power-combining scheme.
The measured efficiency is similar to that achieved with an
equivalent single-chip 190 GHz doubler presented in .
II. SINGLE-WAVEGUIDE POWER-COMBINED SCHEME
The multiplier uses a split-waveguide block design (see
Figs. 1 and 3) with two MMIC chips inserted within the
same transmission waveguide close to its center, where the
electric field of the
mode is maximum. Note that this
topology is electrically and thermally identical to an equivalent
single-chip multiplier driven with half the LO power. At the
input waveguide, each
-plane probe couples one half of the
exciting signal to each MMIC chip. Two quasi-TEM modes,
illustrated in Fig. 2, might propagate the input signal through
thesuspended striplinestowards thediodes locatedattheoutput
waveguide. However, at the
-probes, only the field lines of the
quasi-TEM mode in Fig. 2(b) have the appropriate symmetry
to be excited by the input
symmetry is preserved during fabrication and installation,
this enables the possibility to define a perfect magnetic-wall
boundary at the symmetry plane and simulate only half the
structure (one chip), reducing considerably the design com-
plexity. The nonlinear capacitance of the diodes generates the
second harmonic of the input frequency, which excites the
mode in the output waveguide. The reduced waveguide
channel (210710 ) between the input and output
waveguide acts as a filter that prevents the output
from leaking into the input waveguide. The circuit is completed
with a succession of waveguide sections of different heights
and lengths to provide broadband input and output matching,
as detailed in Fig. 3(b). Each MMIC chip features 6 diodes (12
diodes in total) of about 14
at RF, connected in series at dc, and monolithically integrated
on a 50
-thick GaAs substrate, as shown in Fig. 3(c). The
epilayer doping is approximately
III. CIRCUIT DESIGN AND FABRICATION
mode. Whenever the circuit
in a balanced configuration
The design was driven by the necessity to minimize the im-
pact of possible imprecision in the control of the distance that
separates the two MMIC chips [see Figs. 1 and 3(d)]. This gap
needs to be constant along all the chip size in order not to break
the circuit symmetry, which would result in a dramatic degra-
dation of the multiplier performance, as discussed in detail in
. The shorter the distance, the better input coupling but the
more difficult to assemble the chips with the correct separa-
tion. Hence, a metal-to-metal trade-off distance of 150
been selected to guarantee a precise assembly, as illustrated
Fig. 3. (a) Machined split-block. (b) Close-up photograph of the top half of the
split-block showing input and output matching steps. (c) Multiplier chip layout.
(d) Diagram showing the position of the two chips after assembly, (e) and the
assembly of each individual chip on each half of the block. Dimensions are in
millimeters if not otherwise specified.
in Fig. 3(d). The use of robust 50
dicing and lapping, avoids bending problems during assembly
that would break the symmetry  and guarantees an adequate
heat transfer from the diodes to the block, which is critical at
higher power levels.
The design methodology combines Agilent ADS linear/non-
linear harmonic balance circuit simulation to optimize the
performance of the circuit, with Ansoft HFSS 3-D EM simu-
lation to accurately model the diode geometry and waveguide
structure, as in . Since UMS-BES Schottky process is aimed
for frequency mixers, the characteristics of the available diodes
were not adequate to achieve state-of-the art multiplier per-
formance. The diodes feature very short epilayers (100 nm)
and subsequently low breakdown voltages (
Hence, a biasless design was chosen to guarantee a safe op-
eration regime for the multiplier. In addition, the epilayer
is already fully depleted at 0 volts, resulting in a nearly flat
voltage-capacitance ( - ) characteristics for reverse voltages.
The subsequent loss in capacitance nonlinearity compromises
the attainable efficiency. Under these conditions, only 10%
peak efficiency was expected for the design despite that a 25%
efficiency could be achieved with this topology with more
suitable diodes without the limitation imposed by the short
epilayers . A detailed study on the optimum characteristics
of Schottky multipliers above 100 GHz can be found in .
The nonlinear diode model of ADS cannot well represent
theseparticularoperating conditionsbecauseit doesnotinclude
the impact of the epilayer thickness. Hence, we have developed
rately model the actual response of UMS-BES Schottky diodes.
-thick rectangular sub-
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SILES et al.: A SINGLE-WAVEGUIDE IN-PHASE POWER-COMBINED FREQUENCY DOUBLER AT 190 GHZ3
Fig. 4. Simulated and measured efficiency (top) and input return loss (bottom)
of the 190 GHz dual-chip frequency doubler with 80 mW of input power.
The model represents the diode by means of its equivalent cir-
cuit: A nonlinear capacitance in parallel with a current gener-
ator, and in series with the series resistance. Fitted equations
- characteristics were directly provided by UMS, and
thecurrent-voltage( - ) characteristicshavebeen derivedfrom
The actual dc series resistance of the diodes (
been extracted from -
curves measured under high forward
bias currents to ensure flat-band operation of the diodes (i.e.,
zero junction resistance). A number of tests of various diodes
have been performed to eliminate the impact of the probes re-
sistance on the results. As will be shown later, the predicted
performance with this model is in excellent agreement with RF
The doubler split-block, shown in Fig. 3(a), was machined at
the Rutherford Appleton Lab., UK. As expected, the assembly
was very simple and repeatable, and it was not difficult to well
align the chips preserving the circuit symmetry. Each chip is
fixed face-down with silver epoxy glue to one half of the block
(ground connection) as depicted in Figs. 1 and 3(e).
IV. MULTIPLIER MEASUREMENTS
The source used to test the doubler consisted of a synthe-
sizer tuned in the 29.5–33.83 GHz band followed by an active
tripler, a WR10 isolator, one of two different power amplifiers
to cover either the 88–94 GHz or the 94–102 GHz band, an-
other WR10 isolator and a high-precision attenuator to ensure
a constant input power across the measured frequency band-
width. The input power of the doubler was directly controlled
by the attenuator and monitored using an Erickson Instruments
separately using this calorimeter. The output power of the dou-
bler was measured using the same Erickson PM2 power meter
together with a 1.5 in long WR10 to WR5 waveguide transi-
tion (the measured output power has not been corrected for the
transition loss). For the input return loss measurement, a 10 dB
directional coupler was placed between the attenuator and the
frequency doubler. The reflected input power was measured by
means of an Agilent WR10 W8486A power sensor and an Ag-
ilent N1912A power meter2.
measured for the dual-chip single-waveguide 190 GHz doubler
1Virginia Diodes Inc, 979 2nd Street SE, Charlottesville, VA.
2Agilent Technologies, Inc., 5301 Stevens Creek Blvd., Santa Clara, CA.
when pumped with a 80 mW constant input power across the
measured frequency band (see Fig. 4). Power sweeps between
20 mW and 120 mW input power have also been performed
100 mW, 9.0% @ 80 mW, 8.1% @ 63 mW, 6.7% @ 50 mW and
both conversion efficiency and input return loss proves the va-
lidity of the employed design method and demonstrates the fea-
sibility of the proposed single-waveguide in-phase power-com-
dual-chip doubler demonstrated herein is compact, fixed-tuned
A single-waveguide in-phase power-combined 190 GHz
biasless frequency doubler featuring two identical MMIC
multiplier chips within the same transmission waveguide
has been designed and tested. The achieved doubler perfor-
mance with the available mixer-optimized UMS diodes is
well suited for medium power sources used in test equipment
where the ultimate performance is not necessary. Nevertheless,
state-of-the-art efficiencies could be obtained with this scheme
by using biased Schottky diodes properly optimized for mul-
tiplier operation. This work represents the first demonstration
of this novel circuit topology that increases by a factor of 2
the power handling capabilities of traditional multipliers. This
scheme is simple and reproducible, and we believe that it could
be widely employed in the short term to take advantage of the
increasing LO power at W-band in order to extend the use of
solid-state multiplied LO chains beyond 2 THz. It could also
be potentially applied to power amplifiers.
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