Enhancing dual-Vt design with consideration of on-chip temperature variation
Univ. of Maryland, College Park, MD, USADOI: 10.1109/ICCD.2010.5647619 Conference: Computer Design (ICCD), 2010 IEEE International Conference on
Source: IEEE Xplore
Dual-Vt technology is effective in leakage reduction and has been implemented in industry EDA tools. However, on-chip temperature is regarded as uniformly distributed over the chip, with a pre-assumed value. This assumption does not hold for designs in the deep sub-micron domain as on-chip temperature variation becomes more and more significant. As a result, treating temperature as a constant will either lead to non-optimal design in terms of leakage or unreliable circuit due to potential hot spots that have temperature higher than expected. In this paper, we propose a temperature-aware approach that leverages the on-chip temperature variation and takes into account the coupling effects between leakage and temperature to enhance the leakage reduction of any dual-Vt assignment algorithm. We synthesize and implement Opencore benchmarks using Synopsys tools and TSMC's 65nm low power dual-Vt library. The results show that we are able to improve the performance of a state-of-the-art dual Vt algorithm by an average of 11.2% in leakage saving, a more than 1.4°C drop of peak temperature, and a significant reduction of cells in hot regions without timing failure.
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ABSTRACT: Accurate thermal knowledge is essential for achieving ultra low power in deep sub-micron CMOS technology, as it affects gate speed linearly and leakage exponentially. We propose a temperature-aware synthesis technique that efficiently utilizes input vector control (IVC), dual-threshold voltage gate sizing (GS) and pin reordering (PR) for performing simultaneous delay and leakage power optimization. To the best of our knowledge, we are the first to consider these techniques in a synergistic fashion with thermal knowledge. We evaluate our approach by showing improvements over each method when considered in isolation and in conjunction. We also study the impact of employing considered techniques with/without accurate thermal knowledge. We ran simulations on synthesized ISCAS-85 and ITC-99 circuits on a 45 nm cell library while conforming to an industrial design flow. Leakage power improvements of up to 4.54X (2.14X avg.) were achieved when applying thermal knowledge over equivalent methods that do not.
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