Investigation of current flow during wafer-level CDM using real-time probing

Conference Paper · November 2010with7 Reads
Source: IEEE Xplore
Conference: Electrical Overstress/ Electrostatic Discharge Symposium (EOS/ESD), 2010 32nd


    Using real-time voltage probing and circuit simulation, the stress induced by wafer-level CDM test methods is compared to that of package-level FICDM testers. It is shown that while wafer-level testers can replicate I/O failures, they may not replicate core failures because of differences in the induced current stress.