Automated Design Debugging With Maximum Satisfiability

Vennsa Technol., Inc., Toronto, ON, Canada
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Impact Factor: 1). 12/2010; 29(11):1804 - 1817. DOI: 10.1109/TCAD.2010.2061270
Source: IEEE Xplore


As contemporary very large scale integration designs grow in complexity, design debugging has rapidly established itself as one of the largest bottlenecks in the design cycle today. Automated debug solutions such as those based on Boolean satisfiability (SAT) enable engineers to reduce the debug effort by localizing possible error sources in the design. Unfortunately, adaptation of these techniques to industrial designs is still limited by the performance and capacity of the underlying engines. This paper presents a novel formulation of the debugging problem using MaxSAT to improve the performance and applicability of automated debuggers. Our technique not only identifies errors in the design but also indicates when the bug is excited in the error trace. MaxSAT allows for a simpler formulation of the debugging problem, reducing the problem size by 80% compared to a conventional SAT-based technique. Empirical results demonstrate the effectiveness of the proposed formulation as run-time improvements of 4.5 × are observed on average. This paper introduces two performance improvements to further reduce the time required to find all error sources within the design by an order of magnitude.

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    • "In contrast, we restrict ourselves to verification queries and investigate the impact of substituting arbitrary counterexample producing verifiers with more powerful verifiers which produce counterexamples which are minimal or bounded. Verification techniques have been adapted to provide more meaningful counterexamples [12] [28] [35] [8] for the purpose of aiding design debugging. The key idea is that these more powerful verification engines that provide not just any arbitrary counterexamples but rather a simpler counterexample with respect to some metric can be used for better debugging. "
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    • "Most of the previous works are at transistor-level [5] or gatelevel [6], [7] and they only address automatic error diagnosis for combinational circuits or sequential circuits assuming existence of full scan chain. Although there are some works such as [8], [9] which also propose automated correction , the correction process remains a manual task in most of those works. There are other works targeting RTL designs that try to find and correct errors in RTL descriptions. "
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    • "The designer has to figure out these aspects manually. The approach of [17] improves the resolution in the timing domain -the formulation there is based on Maximum Satisfiability (MaxSAT), i.e., a solver that searches for the maximal subset of clauses being satisfiable. The formulation based on MaxSAT shows, that temporal information helps to explain the faulty behavior. "
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    ABSTRACT: Today, there exist powerful algorithms for automated debugging. Some of the debugging algorithms focus on fault localization while others try to explain the faulty behavior by providing, e.g., correct traces that are similar to a failure trace. SAT-based debugging locates faults, but does not explain the faulty behavior, e.g., some temporal properties of fault candidates are not fully explored. In this work, we study the resolution of SAT-based debugging with respect to its capability to locate faults and to explain faults. A strategy is presented that increases the diagnostic resolution of SAT-based debugging by combining fault localization and fault explanation in one algorithm. The experimental results confirm the strength of the approach and give directions for further research.
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