A 17pJ/bit broadband mixed-signal demodulator in 90nm CMOS
Georgia Electron. Design Center, Georgia Inst. of Technol., Atlanta, GA, USADOI: 10.1109/MWSYM.2010.5518117 Conference: Microwave Symposium Digest (MTT), 2010 IEEE MTT-S International
Source: IEEE Xplore
This paper presents the first fully integrated mixed-signal demodulator incorporating ultra low-power 3mW 3Gsps 3-bit ADCs and a 2mW high-speed real-time digital signal processing in 90nm CMOS that requires neither external synchronization controls nor processing to demodulate up to 3.5Gbps binary phase-shift keying (BPSK) modulated signal. The demodulator is integrated with IQ mixers, 13GHz QVCO, frequency synthesizers and baseband AGC, for an overall power consumption of 60mW from a 1V supply. The entire demodulator chip occupies 1.275×1.19mm2 and enables error free demodulation up to 2.5Gbps and BER of 1E-09 up to 3Gbps. To the best of authors' knowledge, this demonstrates the maximum throughput at minimum power budget among all types of CMOS multi-gigabit demodulators.
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ABSTRACT: This paper presents a very low-power (3mW, 3.9mW) and high-speed (3GS/s, 5GS/s) flash ADC in a deep sub-micron CMOS technology. To save power and area, unnecessary building blocks of ADC are excluded. Optimization of comparator has been fully analyzed to reduce random offsets due to process scaling. Fabricated in 90nm CMOS, the experimental results demonstrate that the ADC occupying 0.0108mm2 active area achieves an effective resolution bandwidth (ERBW) of 1.25GHz and figure-of-merit (FOM) of 0.35pJ/conversion-step. The peak differential non-linearity (DNL) and integral non-linearity (INL) are 0.4LSB. The results obtained in this work is used to satisfy the stringent power requirement of a wireless mixed-signal receiver, specifically suitable for multi-gigabit amplitude shift keying (ASK) and binary phase shift keying (BPSK) demodulations.
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ABSTRACT: In this paper, a low-power high-speed fully integrated mixed-signal quadrature demodulator with an embedded multi-gigabit modem in 90 nm CMOS technology is presented. A wide dynamic-range automatic gain control (AGC) is implemented to avoid clipping distortion experienced by the baseband ADCs. By reusing the power detector circuit within the AGC, analog signal processor is introduced to recover OOK modulated signals up to 2.5 Gb/s for an additional power consumption of 7.5 mW. Integrated with ultra-low-power, 3 mW, 3 GS/s, 3-bit ADCs and high-speed digital modem, the system requires neither external synchronization controls nor processing to demodulate BPSK modulated signals up to 3.5 Gb/s and DBPSK modulated signals up to 1.3 Gb/s. The baseband modem incorporates a mixed-signal, timing-recovery loop to sample the symbols at the optimum SNR based on a high-speed Gardner timing-error detector for an additional power consumption of 14 mW. The analog front-end consists of IQ mixers, a 13 GHz QVCO, frequency synthesizers, and a baseband AGC for an overall power consumption of 52 mW. The entire receiver chip occupies an area of 1.275 × 1.19 mm<sup>2</sup>. To the best of authors' knowledge, this demonstrates the maximum throughput at the minimum power budget and highest level integration among all published wireless multi-gigabit, multi-mode, mixed-signal CMOS receivers.
Conference Paper: A low-jitter low-area PLL with process-independent bandwidth[Show abstract] [Hide abstract]
ABSTRACT: The noise performance of PLL(Phase-Locked Loop) is closely related to the loop bandwidth. Unfortunately, process variation would influence ICP (charge pump current) and KVCO (gain of Voltage-Controlled-Oscillator), and then keep the PLL bandwidth sufficiently far away from the designed value. In this paper, a Digital Auxiliary Method (DAM) is proposed to reduce the change on ICP and KVCO due to process variation and stabilize the loop bandwidth. The PLL design is based on 0.18μm CMOS technology with a 1.8V power supply. Measurement results show that both of the variations are able to be compensated by the Digital Auxiliary Method and keep the bandwidth stable. Depending on the DAM, the output frequency of PLL is 200.68MHz which is 0.34% away from the designed value. The peak-to-peak jitter and rms jitter are 150.2ps and 30.6ps separately.
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