Shape Engineering for Controlled Switching With Nanomagnet Logic

Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, USA
IEEE Transactions on Nanotechnology (Impact Factor: 1.83). 04/2012; 11(2):220 - 230. DOI: 10.1109/TNANO.2010.2056697
Source: IEEE Xplore


We demonstrate that in circuits and systems that comprised of nanoscale magnets, magnet-shape-dependent switching properties can be used to perform Boolean logic. More specifically, by making magnets with slanted edges, we can shift the energy barrier of the device (i.e., so that it is not at a maximum when a device is magnetized along its geometrically hard axis). In clocked systems, we can leverage this barrier shift to make and or or gates that are not majority based. Advantages include reduced gate footprint and interconnect overhead as we eliminate one gate input. In this paper, we report and discuss micromagnetic simulations that illustrate how magnet shape can facilitate nonmajority-gate-based, reduced footprint logic; preliminary fabrication and testing results that illustrate that shape engineering can induce energy barrier shifts; and additional micromagnetic simulations that show other ways in which we might leverage shape in circuits made from nanoscale magnets.

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    • "This layout was created following both theoretical [6] and technological [2] constraints. It is composed by 11 gates, in particular 7 AND and 4 OR [22], and by 7 cross-wires [2]. Moreover, 4 NOT functions are required, but they can be obtained adding 1 nanomagnet in the relative clock zones. "
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    ABSTRACT: In the post CMOS scenario NanoMagnets Logic (NML) has attracted a considerable attention due to its characteristic features. The ability to combine logic and memory in the same device, and a possible low power consumption, allows NML to overcome some of the CMOS intrinsic limitations. However, considering realistic circuit implementations where both theoretical and technological constraints are kept into account, performance could not be reduced with respect to the expectations. The reason lies in the fact that a huge area is wasted with interconnection wires. In this paper we propose a new approach to the conception of magnetic circuits, that we have baptized Domain Magnet Logic (DML). We embed domain walls in NML circuits in a technologically compatible solution, with the aim of improving interconnection performance. We have validated our solution with physical level simulations, and we show the improvements designing as a case study a complex and realistic circuit, a 32 bit Pentium-4 tree-adder. DML logic allows to reduce the circuit area up to 50%, with consequent dramatic improvements on circuit latency and power dissipation. This is a very good result itself, that represents just the tip of the iceberg of the amazing possibilities opened by this innovative approach.
    Full-text · Conference Paper · Aug 2014
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    • "The inverter is simply implemented by an even number of nanomagnets horizontally aligned, because an odd number results in no signal inversion. AND/OR logic gates are obtained cutting one corner of a magnet [13]. The different shape of those magnets gives them a preferential state, which they will leave only when both inputs, from above and below, are up or down, implementing as a consequence an AND/OR logic function. "
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    ABSTRACT: Among emerging technologies Quantum dot Cellular Automata (QCA) plays a fundamental role. Its magnetic version, normally called NanoMagnet Logic (NML), is particularly interesting thanks to the ability to work at room temperature and to mix logic and memory in the same device. Magnetic circuits have also a potential very low power consumption. Unfortunately classic NML circuits are normally driven (clocked) with a current generating a clocked magnetic field, nullifying the possibility to actually obtain low power circuits. We have recently developed a technology-friendly solution, the MagnetoElastic NML (ME-NML), where magnetic circuits are driven through an electric field, and not with a current, drastically reducing the power consumption. In this paper we start to explore the architectural consequences of this new magnetic technology. The analysis is performed using as a benchmark a Galois multiplier, a systolic architecture particularly suited for QCA and NML technologies. The layout is precisely described and the resulting circuit is modeled and simulated using VHDL language. The obtained results are remarkable. The circuit area is reduced by 4 times compared to classic NML approach. This, coupled with the intrinsic lower power consumption due to different clock, leads to a 50 times reduction of power absorption. Moreover the particular structure of magnetoelastic NML allows to define a library of standard cells that can be easily used by designers and automatic layout tools to design circuits, greatly improving future research in this field.
    Full-text · Conference Paper · Jul 2014
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    • "We therefore base our design on 2 input AND/OR gates [6], as shown in Figure 4.A, B. AND/OR gates are made by three magnets, the shape of the central magnet is changed to obtain the desired logic function, the corner is cut so that the magnet get a preferred direction for the magnetization. The advantage of this solution is that inputs come from vertical directions (up or down), where there are no electrodes. "
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    ABSTRACT: In recent years magnetic-based technologies, like NanoMagnet Logic (NML), are gaining increasing interest as possible substitutes of CMOS transistors. The possibility to mix logic and memory in the same device, coupled with a potential low power consumption, opens up completely new ways of developing circuits. The major issue of this technology is the necessity to use an external magnetic field as clock signal to drive the information through the circuit. The power losses due to the magnetic field generation potentially wipe out any advantages of NML logic. To solve the problem new clock mechanisms were developed, based on spin-transfer torque current and on voltage-controlled multiferroic structures that use magnetoelastic properties of magnetic materials, i.e. exploiting the possibility of influencing magnetization dynamics by means of the elastic tensor. In particular the latter shows an extremely low power consumption. In this paper we propose an innovative voltage-controlled magnetoelastic clock system aware of the technological constraints risen by modern fabrication processes. We show how circuits can be fabricated taking into account technological limitations and we evaluate the performance of the proposed system. Results show that the proposed solution promises remarkable improvements over other NML approaches, even though state-of-the-art ideal multiferroic logic has in theory better performance. Moreover, since the proposed approach is technology-friendly, it gives a substantial contribution toward the fabrication of a full magnetic circuit and represents an optimal trade off between performance and feasibility.
    Full-text · Article · Jul 2014 · IEEE Transactions on Nanotechnology
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