Conference Paper

Model Checking PLC Software Written in Function Block Diagram

Mobility Div., Siemens, Braunschweig, Germany
DOI: 10.1109/ICST.2010.10 Conference: Proceedings Third International Conference on Software Testing, Verification and Validation (ICST), At IEEE
Source: IEEE Xplore


The development of Programmable Logic Controllers (PLCs) in the last years has made it possible to apply them in ever more complex tasks. Many systems based on these controllers are safety-critical, the certification of which entails a great effort. Therefore, there is a big demand for tools for analyzing and verifying PLC applications. Among the PLC-specific languages proposed in the standard IEC 61131-3, FBD(Function Block Diagram) is a graphical one widely used in rail automation. In this paper, a process of verifying FBDs by the NuSMV model checker is described. It consists of three transformation steps: FBD→TextFBD→tFBD→NuSMV. the novel step introduced here is the second one: it reduces the state space dramatically so that realistic application components can be verified. The process has been developed and tested in the area of rail automation, in particular interlocking systems. As a part of the interlocking software, a typical point logic has been used as a test case.

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Available from: Hans-Dieter Ehrich
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    • "The formal verification of PLC programs has been tackled by a plethora of work in the last two decades [18]. Most work has been done with regard to the formalization of PLC code according to IEC 61131-3 [19], e.g. for ladder diagrams (LD) [20]–[22], instruction lists (IL) [23]–[25], function block diagrams (FBD) [26], and sequential function charts (SFC) [27]–[30]. More recently, also model-based approaches to the verification of PLCs gained interest [31]– [33]. "
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    • "Programmable Logic Controllers (PLC) are products which are more and more integrated in automated systems, even to perform critical functions; this explains why validation of PLC is gaining an always increasing interest. A possible solution to meet this objective is to apply formal verification techniques ([2]) on the specification of the control logic ([4], [13]) or the PLC code that implements this logic ([1], [5], [6], [9], [12]). These techniques are based on an exhaustive analysis of a state space which represents the specification or the PLC code according to the verification objective. "
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    • "Often the industrial applicability of existing approaches is very limited, primarily due to state space explosion problems. Various solutions to this problem have been attempted [25]. While some of these approaches attempt to verify control applications written in only one language (among the different IEC 61131-3 languages), there are few approaches which work on more than one language [26]. "
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