Conference Paper

A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/shot 5ps TDC in 40nm digital CMOS

IMEC, Leuven, Belgium
DOI: 10.1109/ISSCC.2010.5433840 Conference: Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Source: IEEE Xplore


Digital-intensive PLL architectures emerge [1]-[4], exploiting the benefits of CMOS scaling. This work presents a digital-intensive, reconfigurable 86MHz-12GHz synthesizer. Simple 2-step background calibration enables the use of an area- and energy-efficient 5ps TDC (0.01mm2 and 15-pJ per-shot). Static mismatch calibration lowers the DAC area 4 times. The PLL, featuring digital phase modulation is fully reconfigurable, with loop bandwidth ranging from 0.1-2MHz. At 7GHz, the 0.28mm2 PLL achieves -144dBc/Hz phase noise at 20MHz offset, for 0.56ps jitter in 40MHz bandwidth, consuming less than 30mW.

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