592IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2011
A Digitally-Calibrated Phase-Locked Loop With
Supply Sensitivity Suppression
Shih-Yuan Kao and Shen-Iuan Liu, Fellow, IEEE
Abstract—A digitally-calibrated technique to suppress the
supply voltage sensitivity of a phase-locked loop (PLL) is pre-
sented. The voltage-controlled ring oscillator with an additional
opposite-supply-sensitivity pair is digitally calibrated to sup-
press the supply voltage sensitivity. The circuit is fabricated in a
0.18- m CMOStechnology and the core area occupies 0.235mm?.
The total power consumption is 16.2 mW for a supply voltage of
1.8 V and an operating frequency of 1.5 GHz. For a 100 mV??,
110 kHz sinusoidal waveform noise applied to the supply, the
measured rms jitters without and with calibration are 16.5 and
9.7 ps, respectively, while this PLL works at 1.5 GHz. This PLL
achieves the rms jitter improvement by a factor of 41.2% under
the proposed digitally-calibrated technique.
Index Terms—Band-pass characteristic, digital calibration,
phased-locked loop (PLL), supply voltage sensitivity.
The performance of PLLs has been strictly specified in phase
noise, timing jitter, and reference spur level. In a PLL, the
voltage-controlled oscillator (VCO) is sensitive to process
variations, supply voltage perturbation, and environmental
temperature. In a complex mixed-signal system, when the large
switching transients of the digital circuits occur, the inductive
supply noise (Ldi/dt) will interfere with the noise-sensitive
analog circuits such as VCOs and charge pumps. While the
VCOs suffer from the transient power supply noise, the timing
jitter will degrade. It would be much larger than the jitter
caused by the inherent device electronic noise of the oscillators
such as 1/f noise and thermal noise , . Traditionally, the
passive decoupling capacitance connected between the supply
and ground has been effectively used to suppress power supply
noise. However, it inevitably occupies the additional area in the
Several methods are presented to reduce the power supply
noise impacts on PLLs. In –, the voltage regulator is
adopted to mitigate the power supply noise but the available
voltage headroom is reduced and the bandwidth of the regulator
must be wider than the PLL bandwidth for better supply noise
rejection. The excessive power consumption is also needed. In
HASE-LOCKED LOOPS (PLLs) have been widely used
in modern wireline and wireless communication systems.
Manuscript received August 29, 2009; revisedDecember 01, 2009. First pub-
lished January 29, 2010; current version published March 23, 2011. This work
was supported in part by National Chip Implementation Center (CIC) for chip
fabrication and NSC, Taiwan.
The authors are with the Graduate Institute of Electronics Engineering and
Department of Electrical Engineering, National Taiwan University, Taipei
10617, Taiwan (e-mail: email@example.com).
Digital Object Identifier 10.1109/TVLSI.2009.2039359
–, although the compensation technique with reduced
supply voltage sensitivity is used on the VCO and output clock
buffer, it is actually hard to achieve accurate compensation
because of process variations. In , an adaptive supply com-
pensation technique is employed to reduce the supply voltage
sensitivity even if the process variations exist. However, its
calibration mechanism needs to close and break the PLL alter-
natively and it leads into the long calibration time. In –,
the passive and active decoupling techniques are used but a
large area for passive and active decoupling capacitance is
tally-calibratedopposite-supply-sensitivitypair is presented.To
save the power consumption, the digital calibration circuit is
turned off once the calibration is completed. To reduce the cal-
ibration time, the successive approximation register method is
adopted. This paper is organized as follows. Section II intro-
duces the analysis and suppression technique for supply voltage
sensitivity. The circuit description is presented in Section III.
The experimental results are given in Section IV. Finally, the
conclusions are given in Section V.
II. ANALYSIS AND SUPPRESSION FOR SUPPLY
A. Supply Voltage Sensitivity Analysis
In order to analysis the supply disturbance on the PLL, the
supply noise model of the PLL with a first-order passive loop
filter is shown in Fig. 1. For simplicity, only the supply noise
contribution is considered and the VCO is modeled with two
controlling voltages. One is the control voltage from the loop
filter and the gain is denoted as
voltage and the gain is denoted as
to the output phaseas
. The other is the supply
. Once the fluctuation
noise results in timing jitter increased and the effect is propor-
. The closed-loop transfer function from supply
toin Fig. 1 is derived as
is the VCO’s output phase. The additional phase
1063-8210/$26.00 © 2010 IEEE
KAO AND LIU: DIGITALLY-CALIBRATED PLL WITH SUPPLY SENSITIVITY SUPPRESSION593
Fig. 1. Supply noise model of the PLL.
PARAMETERS FOR THIS PLL
From (2), it exhibits a band-pass characteristic. It is rewritten in
a standard second-order form as
is thecharge-pump currentandis thedivision ratio.
Assume that the supply noise spectrum
Gaussian noise. The contributed power spectrum on the PLL
output is denoted as
sign parameters in Table I, the simulated supply noise transfer
curve is plotted in Fig. 2. The result shows that the center fre-
269 kHz and near to the loop bandwidth of the PLL
is 280 MHz/V before compensation and the
is 15 MHz/V after compensation. Based on the de-
Fig. 2. Simulated supply noise transfer curve.
Fig. 3. (a) Ring VCO delay cell and (b) its supply voltage sensitivities.
3.71 Mrad/s591 kHz . The maximal gain at this
center frequency is 53.5 dB before calibration and 28.1 dB after
calibration, respectively. Besides, the supply voltage sensitivity
of the PLL is defined as
PLL is also suppressed. On the other hand, the 3-dB bandwidth
3.71 Mrad/s 591 kHz of this second-
order band-pass characteristic would determine the frequency
range disturbed by the supply noise.
is reduced, the supply voltage sensitivity of the
602 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2011
Fig. 24. Measured jitter versus operating frequency.
SUMMARY AND COMPARISON
from 16.5 to 9.7 ps after calibration while operating at 1.5 GHz.
So this PLL achieves the rms jitter improvement by a factor of
41.2% under digital calibration mechanism.
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Shih-Yuan Kao was born in Tainan, Taiwan, in
1984. He received the B.S. degree in electrical
engineering from National Cheng Kung University,
Tainan, Taiwan, in 2006. He is currently pursuing
the Ph.D. degree in electronics engineering from
National Taiwan University, Taipei, Taiwan.
His research interests include phase-locked loops
and high-speed CMOS data-communication circuits
for multiple gigabit applications.
in Keelung, Taiwan, in 1965. He received the B.S.
and Ph.D. degrees in electrical engineering from Na-
tional Taiwan University (NTU), Taipei, Taiwan, in
1987 and 1991, respectively.
During 1991–1993, he served as a second lieu-
tenant in the Chinese Air Force. During 1991–1994,
he was an Associate Professor with the Department
of Electronic Engineering, National Taiwan Insti-
tute of Technology. He joined the Department of
Electrical Engineering, NTU, in 1994, where he has
been a Professor since 1998. His research interests include analog and digital
integrated circuits and systems.
Dr. Liu has served as chair of the IEEE SSCS Taipei Chapter in 2004–2008,
which achieved the Best Chapter Award in 2009. He has served as general
chair of the 15th VLSI Design/CAD Symposium, Taiwan (2004) and as
Program Co-chair of the Fourth IEEE Asia-Pacific Conference on Advanced
System Integrated Circuits, Fukuoka, Japan (2004). He was the recipient of the
Engineering Paper Award from the Chinese Institute of Engineers in 2003, the
Young Professor Teaching Award from MXIC Inc., the Research Achievement
Award from NTU, and the Outstanding Research Award from National Science
Council in 2004. He has served as a technical program committee member for
ISSCC in 2006–2008 and A-SSCC since 2005. He was an Associate Editor
for IEEE JOURNAL OF SOLID-STATE CIRCUITS in 2006–2009 and a Guest
Editor for IEEE JOURNAL OF SOLID-STATE CIRCUITS Special Issue in 2008
December. He was an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS
AND SYSTEMS—II: EXPRESS BRIEFS in 2006–2007. He was an Associate Editor
for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
in 2008–2009. He was the Editorial Board of Research Letters in Electronics
in 2008–2009. He is also an Associate Editor for IEICE (The Institute of
Electronics, Information and Communication Engineers) Transactions on
Electronics from 2008. He is an Associate Editor for ETRI Journal, and also an
Associate Editor for Journal of Semiconductor Technology and Science, Korea,
from 2009. He is a member of IEICE.