A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression

Grad. Inst. of Electron. Eng. & Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Impact Factor: 1.36). 05/2011; 19(4):592 - 602. DOI: 10.1109/TVLSI.2009.2039359
Source: IEEE Xplore


A digitally-calibrated technique to suppress the supply voltage sensitivity of a phase-locked loop (PLL) is presented. The voltage-controlled ring oscillator with an additional opposite-supply-sensitivity pair is digitally calibrated to suppress the supply voltage sensitivity. The circuit is fabricated in a 0.18-m CMOS technology and the core area occupies 0.235 mm2. The total power consumption is 16.2 mW for a supply voltage of 1.8 V and an operating frequency of 1.5 GHz. For a 100 mVpp, 110 kHz sinusoidal waveform noise applied to the supply, the measured rms jitters without and with calibration are 16.5 and 9.7 ps, respectively, while this PLL works at 1.5 GHz. This PLL achieves the rms jitter improvement by a factor of 41.2% under the proposed digitally-calibrated technique.

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