Conference Paper

High performance 0.18 μm SOI CMOS technology

IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY
DOI: 10.1109/IEDM.1999.824243 Conference: Electron Devices Meeting, 1999. IEDM Technical Digest. International
Source: IEEE Xplore


A 0.18 μm SOI CMOS technology is presented. Key features in
this technology are: more aggressive gate lithography (equivalent to
0.15 μm half pitch generation) and devices than previously reported
0.18 μm CMOS technology, low dose SIMOX SOI substrate, dual gate
oxide, low ε BEOL insulator, and 7 layer copper metalization.
Inverter delay of less than 6.5 ps has been achieved with this
technology. A POWER4TM test chip was built using the 0.18
μm SOI technology and has demonstrated performance above 1 GHz

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    • "The design of the POWER4 [15] and of newer generations of other IBM high performance microprocessors [1] required considerable integration between synthesis and physical design to manage interconnect effects. The first generation of chips that used the physical synthesis methodology described in this paper, were fabricated in a 0.18-µm CMOS 8S3 SOI (silicon-on-insulator) technology with seven levels of copper wiring [11]. This version of the chip [15] had a clock frequency of greater than 1.3 GHz with a transistor count of 174 million. "
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    ABSTRACT: Integrated logic synthesis and physical design (physical synthesis) continues to play a very important role in high performance microprocessor design methodologies. In this paper, we present the integrated physical synthesis timing closure methodology used in the current generation microprocessors. Physical synthesis techniques were aggressively used as part of logic and placement optimizations for performance, power and area. The design turn around times were significantly reduced and timing convergence was consistently achieved.
    Preview · Conference Paper · Jul 2003
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    ABSTRACT: As SOI technology advances into mainstream, an accurate and predictive compact model is necessary to ensure the success of VLSI chip design. This paper describes a compact model which contributes to the successful implementation of the sophisticated 660 MHz 64-bit PowerPC at its first design. This model captures all important SOI specific device characteristics and circuit behavior properly. The parameter extraction methodology, which is essential in achieving a highly accurate model, will be discussed. Verification results using a 0.18 um (1.5 V) high performance SOI CMOS technology will be presented
    No preview · Conference Paper · Feb 2000
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    ABSTRACT: We describe 100 nm gate length PD-SOI transistors with the best SOI I<sub>on</sub>-I<sub>off</sub> characteristics reported for the 0.18 μm technology generation. SOI inverter delay is 7.4 ps at Vdd=1.5 V and L<sub>gate</sub>=100 nm. Inverter delays show 16% (fanout=1) and 8% Vdd(V) (fanout=4) improvement over comparable bulk CMOS. Scaling analysis for PD-SOI shows a reduced role for junction capacitance and an increased history effect for scaled devices, so that SOI has significantly diminished performance gain relative to bulk CMOS for 50 nm devices (0.1 μm generation)
    No preview · Conference Paper · Feb 2000
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