Both the (5,3) counter and (2,2,3) counter multiplication
techniques are investigated for the efficiency of their operation speed
and the viability of the architectures when implemented in a fast
bipolar ECL technology. The implementation of the counters in
series-gated ECL and threshold logic are contrasted for speed, noise
immunity and complexity, and are critically compared with the
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practical design of a full-adder. A novel circuit technique to overcome
the problems of needing high fan-in input weights in threshold circuits
through the use of negative weighted inputs is presented. The authors
conclude that a (2,2,3) counter based array multiplier implemented in
series-gated ECL should enable a significant increase in speed over
conventional full adder based array multipliers