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Database machines (DBMs) are motivated by the need for high speed query processing. Systolic arrays provide a promising future implementation for DBMs. A systolic architecture for a DBM capable of performing relational algebra operations is introduced in this paper. The array also supports the basic operations for hashing: member, insert and delete, in constant time. A VLSI implementation using a 3υ CMOS technology is analyzed. The systolic array is simple because it employs only one basic cell type. Using only one cell type reduces design time and cost and enhances reliability of DBMs.

Content uploaded by Khaled Elleithy

Author content

All content in this area was uploaded by Khaled Elleithy on Oct 21, 2017

Content may be subject to copyright.

A preview of the PDF is not available

The performance of interconnected distributed-queue dual-bus
(DQDB) networks is studied while the Manhattan street network (MSN) is
being used as the backbone architecture with neural brouters as its
nodes. It is interesting to note that, since the MSN topology is
logically equivalent to a multichannel ring network, it may be easily
adapted to operate as a token ring-of course, with multiple tokens-or
token mesh network at heavy load conditions. Relevant performance
measures using both an analytical method and simulation are also
included

The combination of systolic array processing techniques and VLSI fabrication promises to provide modularity in the implementation of matrix operations for signal-processing with throughput increasing linearly with the number of cells utlized. In order to achieve this, however, many design tradeoffs must be made. Several fundamental questions need to be addressed: What level of complexity (control) should the processor incorporate in order to perform complicated algorithms? Should the control for the processing element be combinatorial logic or a microprocessor? The broad application of a systolic processing element will require flexibility in its architecture if it is to be produced in large enough quantities to lower the unit cost so that large arrays can be constructed. In order to have a timely marriage of algorithms and hardware we must develop both concurrently so that each will affect the other. A brief description of the hardware for a programmable, reconfigurable systolic array test-bed, implemented with presently available integrated circuits and capable of 32 bit floating point arithmetic will be given. While this hardware requires a small printed circuit board for each processor, in a few years, one or two custom VLSI chips could be used instead, yielding a smaller, faster systolic array. The test-bed is flexible enough to allow experimentation with architecture and algorithms so that knowledgeable decisions can be made when it comes time to specify the architecture of a VLSI circuit for a particular set of applications. The systolic array testbed system is composed of a minicomputer system interfaced to the array of systolic processor elements (SPEs). The minicomputer system is an HP-1000, with the usual complement of printer, disk storage, keyboard-CRT, etc. The systolic array is housed in a cabinet approximately 28″x19″x21″. The interface circuitry uses a single 16-bit data path from the host HP-1000 to communicate data and commands to the array. Commands and data are generated in the HP-1000 by the operator using interface programs written in FORTRAN. Algorithms can be conceived, put into a series of commands for the systolic array processor, and tested for validity. Data computed in the array can be read by the host HP-1000 and displayed for the operator. The use of a general purpose minicomputer as the driver for the systolic array gives unlimited flexibility in developing algorithms. Through the use of interface routines, algorithms can be tried, evaluated, change and tried again in a few minutes. Also, in cases where the output must be manipulated and fed back into the array, the manipulation of the data can be done either in the host using the high order language capability (for optimum flexibility), or in a dedicated microprocessor interfacing the systolic array to the host (for optimum speed).

A new tree-structured machine (suitable for VLSI implementation) that solves a large class of searching problems is described. A set of N elements can be maintained on an N-processor version of this machine such that insertions, deletions, queries and updates can all be processed in 2 lg N time units. The queries can be very complex, including problems arising in ordered set manipulation, data bases, and statistics. The machine is pipelined so that M successive operations can be performed in M minus 1 plus 2 lg N time units. Both the basic machine structure and the actual implementation of the machine are studied.

In the near future, we can expect a great variety of languages to be proposed for interrogating,and updating data bases. This paper attempts to provide a theoretical basis which may be used to determine how complete,a selection capability is provided in a proposed,data,sublanguage independently,of any host language in which,the sublanguage,may,be embedded. A relational algebra and a relational calculus are defined. Then, an