Conference Paper

A Computational Reflection Mechanism to Support Platform Debugging in SystemC.

DOI: 10.1145/1289816.1289838 Conference: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007
Source: DBLP


System-level and Platform-based design, along with Trans- action Level modeling (TLM) techniques and languages like SystemC, appeared as a response to the ever increasing com- plexity of electronics systems design, where complex SoCs composed of several modules integrated on the same chip have become very common. In this scenario, the exploration and verification of several architecture models early in the design flow has played an important role. This paper pro- poses a mechanism that relies on computational reflection to enable designers to interact, on the fly, with platform sim- ulation models written in SystemC TLM. This allows them to monitor and change signals or even IP internal register values, thus injecting specific stimuli that guide the simula- tion flow through corner cases during platform debugging, which are usually hard to handle by standard techniques, thus improving functional coverage. The key advantages of our approach are that we do not require code instrumenta- tion from the IP designer, do not need a specialized SystemC library, and not even need the IP source code to be able to inspect its contents. The reflection mechanism was imple- mented using a C++ reflection library and integrated into a platform modeling framework. We evaluate our technique through some platform case studies.

Download full-text


Available from: Cristiano Araujo
  • Source
    • "A novelty introduced by ReSP lies in the Python wrapper generation for SystemC and TLM components. In previous works [7], [8], [10], [27], [29], the developer had to write special interface files or use specific classes in order to add components to the framework's database. Moreover, only the components' characteristics described in those interface files could be used by the simulator. "
    [Show abstract] [Hide abstract]
    ABSTRACT: This paper presents ReSP (Reflective Simulation Platform), a Transaction-Level multi-processor simulation platform based on SystemC and Python; SystemC is a standard language for system modeling and verification, and Python provides the platform with reflective capabilities. These are employed to give the designer an easy way to specify the architecture of a system, simulate the given configuration and perform automatic analysis on it. ReSP enables SystemC and Python interoperability through automatic Python wrapper generation. We show that the overhead associated with the Python intermediate layer is around 1%, therefore execution speed is not compromised. The advantages of our approach are: (a) easy integration of external IPs (b) fine grain control of the simulation (c) effortless integration of tools for system analysis and design space exploration. A case study shows how the platform can be extended to support system reliability assessment.
    Full-text · Conference Paper · Apr 2008
  • [Show abstract] [Hide abstract]
    ABSTRACT: The complexity of modern hardware design has created the need for higher levels of abstraction, where system modeling is used to integrate modules into complex System-on-Chip (SoCs) platforms. SystemC, and its TLM (Transaction Level Modeling) extensions, have been used for this purpose mainly because of their fast prototyping and simulation features, which allow for early design space exploration. This paper proposes an approach to explore and interact with SystemC models by means of an introspection technique known as Computational Reflection. We use reflection to implement a white-box introspection mechanism called ReflexBox. We show that ReflexBox is a fast, non-intrusive technique that can be used to dynamically gather and inject stimuli into any SystemC module, without the need to use a proprietary SystemC implementation, change the SystemC library, instrument or even inspect the module source code. Our approach can be used to support many different verification tasks like platform debugging, performance evaluation and communication analysis. To show ReflexBox effectiveness we used it in three platforms case studies to address tasks like register inspection, performance analysis and signal replaying for testbench reuse. In all cases we assumed no source code availability and measured the impact on the overall platform performance.
    No preview · Article · Mar 2012 · Design Automation for Embedded Systems
  • [Show abstract] [Hide abstract]
    ABSTRACT: Post-partitioning verification has to deal with abstract data, implementation artifacts, and the order of events may not be preserved in the DUV due to the concurrency treatment in the golden model. Existing techniques are limited either by the use of greedy heuristics (jeopardizing verification guarantees) or by black-box approaches (impairing observability). This work proposes a novel white-box technique that overcomes those limitations by casting the problem as an extended bipartite graph matching. By relying on proven properties, solid verification guarantees are provided. Experimental validation was performed upon platforms built around contemporary real-life applications.
    No preview · Conference Paper · Aug 2009
Show more