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Fast dynamic simulation of VLSI circuits using reduced order compact macromodel of standard cells
Abstract
This paper presents a dynamic simulation methodology using a reduced order compact macromodel of standard cells. The standard cell macromodels are formulated with a smaller number of state variables compared to an equivalent transistor-level implementation. This results in significant speed-ups over transistor-level simulation for large scale circuits. Such reduction in state variables also reduces memory usage. The macromodels are based on transistor equations, and simulation using these models produces results in excellent agreement (delay errors below 1%) with transistor-level simulation results. Various examples showing 1.5x−100x reduction in dynamic simulation time and 1.5x−2.8x reduction in memory usage are presented.
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Fault injection techniques have been proposed recently to early analyze the dependability characteristics of analog circuits. The aim of this paper is to compare SPICE level and high level analyses for SET-like faults injections on a PLL mixed analog-digital circuit. Advantages and drawbacks will be discussed, as well as the accuracy of the high level modeling with respect to low level effects of transients due for example to energetic particle hits.
The problem of multiple-input switching (MIS) has been mostly ignored by the timing CAD community. Not modeling MIS for timing can result in as much as 100% error in stage delay and slew calculation. The impact is especially severe on stages immediately after a bank of flops, where the inputs have a high probability of arriving simultaneously. Other problems such as modeling of interconnect loads, complex (nonlinear/nonmonotonic) input waveforms, power-droop impact on cell delay, nonlinear input capacitances, delay variations due to cross-capacitance, etc. are also known sources of error. In this paper, we introduce the multi-port current source model (MCSM). MCSM can efficiently handle an arbitrary number of simultaneously switching inputs, including single-input switching (SIS). Moreover, MCSM is comprehensive in that other modeling problems associated with delay and noise computation are elegantly covered. We demonstrate the applicability of MCSM on a large 65 nm industrial test-case. For cells experiencing MIS, the model yields delay and slew-rate errors within plusmn5% for 88.3% and 93.0% of the cases, respectively. We also present data that show that MCSM is an effective receiver model which captures active loading effects without incurring significant additional error. MCSM makes combined cell-level timing, noise, and power analysis a possibility
In recent years, there has been a trend among digital and analog circuit designers towards three-dimensional integration. There has been some debate regarding the applicability of 3-D technology to general logic circuits, especially with regard to thermal issues. We examine process variations on the same layer, across layers, and cross-chip variations. We show how the performance of each layer of the 3-D chip varies with temperature, and demonstrate the effect of heat pipes on circuit performance.
The use of behavioural modelling for operational amplifiers has
been well known for many years and previous work has included modelling
of specific fault conditions using a macro-model. In this paper, the
models are implemented in a more abstract form using an Analogue
Hardware Description Language (AHDL), VHDL-AMS, taking advantage of the
ability to control the behaviour of the model using high-level fault
condition states. The implementation method allows a range of fault
conditions to be integrated without switching to a completely new model.
The various transistor faults are categorised, and used to characterise
the behaviour of the HDL models. Simulations compare the accuracy and
speed of the transistor and behavioural level models under a set of
representative fault conditions
The use of heavy-ion radiation from 252Californium as a fault injection method for experimental validation of dependable computing systems is described and discussed. Heavy ions from 252Cf can cause transient faults as they pass through depletion regions in integrated circuits. Irradiation of a circuit must be performed in a vacuum. A design of a portable miniature vacuum chamber which contains one integrated circuit and a 252Cf source is presented. The vacuum chamber can be plugged directly into an IC socket of the same type as the irradiated circuit uses. For an effective system validation, the fault injection method used must cause a variety of errors in the irradiated circuit. Results from irradiation of the MC6809E 8-bit microprocessor are presented. They show that errors occurred on all output pins of the microprocessor, and that both single and multiple bit errors were observed. Sensitivity to heavy ion radiation from 252Cf for various IC technologies is discussed briefly.
fREEDAtrade is capable of transient, wavelet, harmonic balance, DC and AC analysis of circuits. Of these it is transient analysis has the greatest capability of revolutionizing the ability to design of RF circuits. fREEDAtrade uses a number of new strategies to achieve a dynamic range in transient simulation exceeding 160 dB, large signal noise analysis, modeling of oscillator phase noise, handling arbitrarily long time delays, and capturing mixed-physics. For the first time the overall philosophy behind fREEDAtrade is outlined with particular attention to topology
Analog cells immune to conducted radio frequency interference (RFI) can be obtained by designing low-distortion circuits. This can be achieved by using metallic oxide semiconductor (MOS) transistors instead of bipolar transistors. Choosing circuit topologies that account for predistortion and postdistortion can also help obtain desired immunity. With regard to operational amplifiers, controlling slew-rate symmetry can greately reduce offset voltage. Digital circutis are very susceptible to pulsed interference, whereas they offer good immunity to conducted RFI.
This paper outlines a general method to analyze circuits with the minimum number of non-linear unknowns and error functions. For some cir-cuits, this number is much smaller than the size of the nonlinear system resulting from applying con-ventional formulations. The linear subnetwork is described by a modified nodal admittance matrix. Robustness is obtained by a state-variable approach. We show the derivation of different transient anal-ysis equations based on wavelets, convolution and time-marching techniques from a general set of equa-tions.
The critical charge, Q crit , of a memory array storage cell is defined as the largest charge that can be injected without changing the cell's logic state. The Q crit of a Schottky-coupled complementary bipolar SRAM array is evaluated in detail. An operational definition of critical charge is made, and the critical charge for the cell is determined by circuit simulation. The dependence of critical charge on upset-pulse wave shape, statistical variations of power supply voltage, temperature gradients, manufacturing process tolerances, and design-related influences due to word- and drain-line resistance was also calculated. A 2× range in Q crit is obtained for the SRAM memory array cell from simulations of normal (±3σ) variations in manufacturing process tolerances, the shape of the upset current pulse, and local cell temperatures. Using SEMM, a 60× variation of the soft-error rate (SER) is obtained for this range in Q crit . The calculated SER is compared to experimental values for the chip obtained by accelerated testing. It is concluded that a range in values of the critical charge of a cell due to normal manufacturing and operating tolerances must be considered when calculating soft-error rates for a chip.