Conference Paper

A New Paradigm for Low-power, Variation-Tolerant Circuit Synthesis Using Critical Path Isolation

DOI: 10.1145/1233501.1233628 Conference: 2006 International Conference on Computer-Aided Design (ICCAD'06), November 5-9, 2006, San Jose, CA, USA
Source: DBLP

ABSTRACT

Design considerations for robustness with respect to variations and low power operations typically impose contradictory design requirements. Low power design techniques such as voltage scaling, dual-Vth etc. can have a large negative impact on parametric yield. In this paper, we propose a novel paradigm for low-power variation- tolerant circuit design, which allows aggressive voltage scaling. The principal idea is to (a) isolate and predict the set of possible paths that may become critical under process variations, (b) ensure that they are activated rarely, and (c) avoid possible delay failures in the critical paths by dynamically switching to two-cycle operation (assuming all standard operations are single cycle), when they are activated. This allows us to operate the circuit at reduced supply voltage while achieving the required yield. Simulation results on a set of benchmark circuits at 70nm process technology show average power reduction of 60% with less than 10% performance overhead and 18% overhead in die-area compared to conventional synthesis. Application of the proposed methodology to pipelined design is also investigated.

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Available from: cecs.uci.edu
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    • "Prior work that addresses variability can be classified into (i) statistical design approaches [32] [13] [23], (ii) post silicon compensation and correction [18] [25] [39], and (iii) variation avoidance [12] [5] [16]. Our work differs in that it addresses hardware variability in the operating system layer. "
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    • "In this paper we propose algorithmic modifications for two different motion estimation algorithms that work well with probabilistic computing and can save up to 70% of energy for different kinds of motion estimation algorithms. Also, the proposed approaches of a parallel motion estimation architecture for error correction [23], input dependent variable computational clock cycles [26] [27] [28] [29] and voltage scalable metafunction design [29] all require significant computational overheads whereas the modifications proposed in this paper have far less computational overheads. One of the modifications suggested in this paper requires a parallel computing architecture; despite the use of a parallel architecture, the use of the parallel architecture is minimal and, hence, computational overhead is minimal. "

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    • "II. RELATED WORK Prior work that addresses variability can be classified into (i) statistical design approaches [25] [9] [17], (ii) post silicon compensation and correction [12] [18] [32], and (iii) variation avoidance [8] [3] [11]. Our work differs in that it addresses hardware variability in the operating system layer. "
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    ABSTRACT: Instance and temperature-dependent leakage power variability is already a significant issue in contemporary embedded processors, and one which is expected to increase in importance with scaling of semiconductor technology. We measure and characterize this leakage power variability in current microprocessors, and show that variability aware duty cycle scheduling produces 7.1× improvement in sensing quality for a desired lifetime. In contrast, pessimistic estimations of power consumption leave 61% of the energy untapped, and datasheet power specifications fail to meet required lifetimes by 14%. Finally, we introduce a duty cycle abstraction for TinyOS that allows applications to explicitly specify lifetime and minimum duty cycle requirements for individual tasks, and dynamically adjusts duty cycle rates so that overall quality of service is maximized in the presence of power variability.
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