A Cost-Efficient Bit-Serial Architecture for Sub-pixel Motion Estimation of H.264/AVC
DOI: 10.1109/IIH-MSP.2008.280 Conference: 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2008), Harbin, China, 15-17 August 2008, Proceedings
This paper presents a new VLSI architecture for sub-pixel motion estimation in H.264/AVC encoder. It is based on an interpolation-free algorithm that causes a high level reduction on memory requirement, hardware resources and computational complexity. A high performance, bit-serial pipeline architecture is proposed for quarter-pixel accurate motion estimation which supports real-time H.264 encoding. Due to the bit-serial, modular and reusable architecture, it provides significant improvement in area cost (at least 39%) and increases the macroblock processing speed almost 6 times when compared with the previous designs. The proposed architecture is suitable for portable multimedia devices where the memory and power consumption are limited.
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ABSTRACT: Estimating motion between two frames of a video sequence, up to sub-pixel accuracy, is a critical task for many image processing applications. Efficient block matching algorithms were proposed for motion estimation up to pixel accuracy. Applying these fast block search algorithms to up-sampled and interpolated frames can produce good results but with significant increase in computations. To reduce the number of search points, and therefore the computational cost, quadratic prediction was proposed earlier to predict the location of minimum block matching error, and then to limit the search window to the vicinity of the predicted location. In this paper we investigate the typical behavior of block matching error surface and propose an improved higher order prediction that models the error surface more accurately, utilizing additional local image behavior. Initial experiments have proved promising results of about 50% more improvement in PSNR compared to quadratic prediction with only a marginal increase in the computational cost.
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ABSTRACT: The sub-pixel motion estimation (SME), together with the interpolation of reference frames, is a computationally extensive part of the H.264 encoder that increases the memory requirement 16-times for each reference frame. Due to the huge computational complexity and memory requirement of the H.264 SME, its hardware architecture design is an important issue especially in high resolution or low power applications. To solve the above difficulties, we propose several optimization techniques in both algorithm and architecture levels. In the algorithm level, we propose a parabolic based algorithm for SME with quarter-pixel accuracy which reduces the computational budget by 94.35% and the memory access requirement by 98.5% in comparison to the standard interpolate and search method. In addition, a fast version of the proposed algorithm is presented that reduces the computational budget 46.28% further while maintaining the video quality. In the architecture level, we propose a novel bit-serial architecture for our algorithm. Due to advantages of the bit-serial architecture, it has a low gate count, high speed operation frequency, low density interconnection, and a reduced number of I/O pins. Also, several optimization techniques including the sum of absolute differences truncation, source sharing exploiting and power saving techniques are applied to the proposed architecture which reduce power consumption and area. Our design can save between 57.71–90.01% of area cost and improves the macroblock (MB) processing speed between 1.7–8.44 times when compared to previous designs. Implementation results show that our design can support real time HD1080 format with 20.3 k gate counts at the operation frequency of 144.9 MHz.
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