Conference Paper

FPGA-based Testing Strategy for Cryptographic Chips: A Case Study on Elliptic Curve Processor for RFID Tags

DOI: 10.1109/IOLTS.2009.5196009 Conference: 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal
Source: DBLP


Testing of cryptographic chips or components has one extra dimension: physical security. The chip designers should improve the design if it leaks too much information through side-channels, such as timing, power consumption, electric-magnetic radiation, and so on. This requires an evaluation of the security level of the chip under different side-channel attacks before it is manufactured. This paper presents an FPGA-based testing strategy for cryptographic chips. Using a block-based architecture, a testing bus and a shadow FPGA, we are able to check information leakage of each block. We describe this strategy with an Elliptic Curve Cryptosystem (ECC) for RFID tags.

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