An I-IP based approach for the monitoring of NBTI effects in SoCs

Conference Paper · June 2009with4 Reads
DOI: 10.1109/IOLTS.2009.5195977 · Source: DBLP
Conference: 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal


    In this paper we present a design for reliability methodology, with the goal of reducing the impact of transistor VTH degradation due for example to phenomena such as NBTI. It uses infrastructure IPs (I-IPs) featuring a self compensation scheme that automatically detects transistor aging effects and illustrates the design for test infrastructure used to make the SoC/System aware of the NBTI effects. This scheme is conceptually validated by using multi-level simulation and models. The discussion of possible exploitation models completes the paper.