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All content in this area was uploaded by Khaled Elleithy

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Content uploaded by Khaled Elleithy

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All content in this area was uploaded by Khaled Elleithy

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A FRAME-WORK FOR HIGH LEVEL SYNTHESIS

OF DIGITAL ARCHITECTURES FROM ,+-RECURSIVE ALGORITHMS

Khaled M. Elleithy and Magdy A. Bayoumi

The Center For Advanced Computer Studies

University of Southwestern Louisiana

Lafayette, LA 70504, U.S.A.

ABSTRACT

The major drawback of reported high level synthesis

techniques is their limited applicability to a specific class of

algoriehms without extendibility to general algorithms and

the lack of a formal approach to prove the correctness of

the such techniques. In this paper, we introduce a novel

approach for high level synthesis from p-recursive alg+

rithms. Two features are provided by the approach: com-

pleteness and correctness. Completeness means the ability

to use the approach for any general algorithm. Correctness

is achieved by using a set of transformations that are

proved to be correct. A formal framework for the synthesis

procedure has been developed which can be easily

automated. A given algorithm will be represented in a new

developed language termed Algorithm Specification

Language (ASL). ASL has the ability to describe any gen-

eral algorithm. An automatic procedure is used to

transform an ASL representation into a specific realization

specification using a correctness preserving set of transfor-

mations. The realization format is based on representing

the digital architectures by a Realization Specification

Language(RSL).

1.

Introduction

Early works in high level synthesis field were basi-

cally require the input to have a structural description.

CMU-DA [HY82, KT83, K084] require the input to be

described using Instruction Set Processor Specification

(ISPS)[BA81). The problem with such approachs is the

requirement to know the target architecture in advance in

order to have the structural description.

Synthesising a general algorithm from a behavioral

description using a programming like language have been

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0 1990

ACM

089791-348-5/90/0002/0305 $1.50 305

reported in [TR87, TK89]. Flamel[TR87] uses Pascal as a

behavioral description language. A number of restrictions

are imposed on the input description: the description

should be parameterless and nonrecursive, certain data

types are only allowed, and certain arithmetic operations

are not allowed. HARP[TK89] uses Fortran as the

behavioral description language. The designer is responsi-

ble for determining the facility’s word length and the com-

position of units. Restrictions are imposed on the input

specification such as: only certain data types are allowed,

subroutine and function calls are not allowed, and certain

functions are omitted. Communicating Sequential

Processes (CSP) IS used as a description language by Phi-

lips (NB88, BM88]. Using a CSP as a description language

means that the designer is responsible for specifying the

operations sequencing and communications among different

units. Applicative languages have been used for behavioral

description of an algorithm. Johnson[J083] has presented

an approach for transforming a system described in the

form of linear recursion equations to digital designs.

Most reported techniques suffer some or all of the

following disadvantages:

Ill

PI

PI

PI

(51

Some systems are not suitable for large problems

since it depends on solving NP-C problems

(Emerlad[TS84] -clique problem).

Some

systems require to know

the

target architecture

in

advance in order to have the structural descrip-

tion [HF82, PF82, AG83, KG83, KT83, K084,

KG85].

A number of restrictions are imposed on the input

description (FlameI[TR87], HARP[TK89]).

Certain phases of the design process are not

automated due to the lack of algorithms to

transform between different representations. Such

limitations require the designer’s responsibility for

designing these phases (HARP[TK89]).

The designer is responsible for specifying the opera-

tions sequencing and communications among

different units [NE%88, BM88].

[6] Some systems are limited to a special class of algo

rithms [Jc)83, QU84, RA85]

High level synthesis approaches don’t only suffer

from the previous drawbacks, but they don’t also address

two focal points: Completeness and

Correctness.

Complete-

ness means the ability to use the approach for any general

algorithm. Correctness is achieved by using a set of

transformations that are proved to be correct. The pro

posed framework for synthesizing any algorithm is as fol-

lows:

[I] The given algorithm is represented in the new

language ASL which is capable of representing any

algorithm using a limited number of constructs.

[2] A transformational method is given to transform an

algorithm in ASL to RSL representation. The RSL

version specifies the components and connectivity of

the digital architecture that realizes the algorithm,

Every construct in ASL has an isomorphic represen-

tation in RSL, which is the basis of the automated

transformation.

2. Algorithm Specification Language (ASL)

The idea of representing an algorithm using a func-

tional

representation

was introduced by Kleene[KE36] in

which any function from numbers(strings) to

numbers(strings) can be constructed using very primitive

functions and combining them in a specific manner. Our

approach for specifying an algorithm depends on using /.L-

recursive

functions

as a frame-work. We have the follow-

ing constructs:

[I] Initial functions

IF N is the space of natural numbers, NK is the k-space

of natural numbers, and kEN, then a function is initial if

and only if:

(a) It is a Zero function(<) from No to N such that:

co = 0.

(b) It is the Projection function(v) from Nk to N such

that:

~It(arg,,afg,,....,argk) = a%

(c) It is the successor function(X) from N to N such that:

A(n) = n+l.

[2] Recursion

A function is called recursive:

(a) If it is an initial function.

(b) If it can be obtained from initial functions by applying

some sequence of the following two operations:

(i) Composition: if zl,zs, . . ,zm are n place functions, y

is m place function, then z is a n place function defined as

follows: 2 ‘,Y(ZlA I”‘, Gn).

(ii) Recursion: if z is n place function, z is a n+l place

function and y is n+2, then z is defined as follows:

z(am, . . . ,wh, 0 ) - z(avh . . ,avn)

z(argl, . ,arg,, m+l ) =

g(avh . . . ,arg,,m, .darg,, . . . ,av,, m ))

Although the previous definition of a recursive

function

is

very powerful in a sense that it can be used to represent

any practical function, it is not sufficient to represent any

computable function[LP81]. The class of all computable

functions is called

p-recusive

functions.

[3] Unbounded minimization

Let z be a n+l-place function, then the unbounded

minimization of z is an

n

place function($(z)) defined as:

f(avbaw2, . . . ,avn)

- min m (6.t z(arg,,arge, . s * ,atgn,m) = 0)

- 0 if m does not ezists

The previous definition of functions obtained by

unbounded minimization is not computable since we don’t

know if there exists an m that satisfies the condition. If

such an m does not exist this means that any machine

used to compute f will not halt and will run forever. This

uncomputability problem with functions obtained by

unbounded minimization can be resolved by specifying an

upper bound for m which leads to the bounded minimiza-

tion which is computable no matter how large is m This

new restriction for

m

reduces our capability of specifying a

genera1 function. A sub-class of functions obtained using

unbounded minimization called Regular functions is

sufficient for specifying any computable function.

[4] Regular Functions

A function is regular if El an

m

V

arg,,

v

l<i<n

and

nEN, such that:

g(argbam, . . ,arh,O) - 0.

[5] P-Recursion

A function is called

mu -recursive :

(a) If it is recursive.

(b) If it is obtained from recursive functions by a finite

sequence of composition, recursion and unbounded minimi-

zation.

[8] G6del Numberings:

Although our definition of recursive functions is from

numbers to numbers, it can be used for functions from

strings(numbers) to strings(numbers). The method for

extending the language to be capable for dealing with func-

306

tions defined over strings is to use some kind of encoding

to represent strings as numbers. Godel[LP81] numbering is

used for this kind of encoding. Let C be a finite set of sym-

bols used to represent

a

string, and (Y be the number of

symbols in C. Let C be as follows:

c - (Q1, . . . . , a,}

A mapping function + that maps C to N is defined as fol-

lows: O(q) = i I~igz

The Godel number(n) of a string WEC’ and a length

1 EN

is computed as follows:

qw1w2. . WI) = &Pqw,)

&=I

[7] Basic functions

Our specification language at this point depends on three

initial functions and three operations that can be applied

in a certain sequence to obtain any computable function,

Although this language of specification is complete but it is

very tedious to represent a large function. A library of

basic functions can be defined starting from the initial

functions to be used in the definition of larger functions,

This approach is useful for building an automated system

for synthesising. All basic functions that may be ready for

usage can be defined using our system of specification.

This

technique supports a hierarchical design methodology in

the sense that the specification can be stopped at any level

as long the lower levels are previously defined. When Basic

functions

are used to represent another functions, each

Basic

fmction

is written in a t&J .

Example

If we consider that pro is a basic function, then the fat

torial (pow(n ,m)) is defined as follows:

pow(n,O) = X(W).

Pro

1s(w1,w2t’w?s)

=

m (~8(a~gl,arg2,a~gS),Ts9(a~gl,argz,a~gs))

pow(n,m+l) = pro,$n,m,pow(n,m)).

From the previous definition we see that we do not express

the function pow in terms of

initial functions,

but we use

&?i as a

basic function,

which may be expressed explicitly

in a library of basic functions.

3. Realization Specification Language (RSL)

The realization introduced here is described at the

architectural level. The specification describes two elements

of a circuit: the components and the connectivity. The

physical parameters of the circuit are not addressed at this

level of specification. The timing is not expressed explicitly,

but implicitly in terms of

registers

The symbol p is used

to represent a register. If it is required to initialize the

register to a certain value 8, then this is represented as pg.

Now we will show how the different component of ASL can

be expressed at

Language( RSL ). the Realization Specification

[l] If unit is a certain component that is used in the sys-

tem, and inp is any input for

unit,

then we can use this

input explicitly using the following syntax:

uni&

Also an output(out) of unit can beused as follows:

unit Out

[2] Identifiers starting with a upper case letter are used to

represent units that will be further expressed at lower lev-

els Identifiers starting with an lower case letters will be

used to express Basic functions. Identifiers starting with

lower case letters are used also to represent constants,

while those starting with upper case letters are used to

represent temporary variables used in computation.

[3] Register: If it is required to use a register (Y that is ini-

tialized to a value 8, then this is expressed as pj. As an

Example the expression p;s~c(1) means that suc unit has

the register 1 connected to its input with a value 2 as the

register initial value. Init statement is a RX expression

that can be used separately to express that register

ulhpa is

initialized to value fi as follows:

Init (cuJ3)

Another version of

Znit

can be used to denote the initiali-

zation of more than one register at the same time, this is

represented as follows:

Initp(~& ; ~2,/32; . ; ~n,Bn)

The previous statement means that n registers are initial-

ized in parallel such that register o1 is initialized with the

value pi, register cy2 is initialized with the value p2, etc...

Notice that using registers is the only way to represent

time in our circuits.

It is assumed that all registers are syn-

chronized using a global clock.

[4] Constant values are expressed using registers. If it is

required to have a constant value (c) in the circuit, then

this is represented as

pC.

If it is required to represent the

zero function directly the foliowing specification is used:

Result - zero

zero Rcsdy - ~ewontrol

[5] The representation of functional units and control sec-

tion is presented in section 4.

4. Transformation Algorithm

The transformation algorithm is based on using

a

one-toone mapping procedure. The algorithm takes an

ASL representation and transform each ASL’s construct to

an equivalent RSL representation and an equivalent archi-

tecture implementation. We show in this section how each

of the ASL’s six constructs is implemented.

[l]

Projection

function is implemented using the circuit

shown in Figure 1.

Argn ,n

) Control >

1 log n

T

T

Result

Ready

Argl

Argn

Control

Fig. 3. Composition Function

Result

Ready

Fig. 1. Projection Function.

A multiplexer is used to choose the input number i from k

inputs. The multiplexer used is an (k ,[log kl multiplexer.

n 3

The operation of the multiplexer is controlled by a control )

line called control. An output line called ready is used to

g@rqready ) Control pn+l

) Eq&?

, Ready

1

indicate that the circuit has finished its operation. This is

represented in RSL as follows:

Result = muz(argl , . . . . , argb # i)

muxRcad~ -

muxcdd

[2]

Successor

function is implemented using the circuit

shown in Figure 2.

p+: F, p y:’

Fig. 2. Successor Function.

An adder is used to implement the ~ucce~~~r function. This

is represented in RSL as follows:

Result - sue(n)

SuCRtd = SUCControl

[3] Composition

function is implemented using the circuit

shown in Figure 3. The representation in RSL as follows:

Result = Comp(xl,....,x, # y)

compRc4 I And(x,“““““’ , xPCo”trol , ,,.,.% control)

Notice that

And

represents the logical and, and it is con-

sidered as a Basic function.

[4] Recursion

is represented using the circuit shown in

Figure 4. The component

eq?

is used to test if the inputs

are equal, it is represented in RSL as follows:

Result = eq?( arg 1 , arg,)

The RSL representation of the circuit for recursion is as

Fig. 4. Recursion Implementation.

follow

Initp(0,m ; l,urg, ; 2,urge; . . . ;

n,urg,)

su;~o;~+7~biJ~;

(1)

(2)

(3)

Ready

- eq?(1 ,

m) (4)

Result - comp(arg,I,p;(+$, Result # y) (5)

Equation 1 is used to indicate that we use n registers to be

initialized with the arguments of the h component and a

register for the constant m. Equation 2 means that the

unit Sue which is a basic function has its input

control

connected to the

ready

output of the unit computing g(n)

to be sure that I is not incremented until g(c) is com-

puted. Equation 3 is used to represent the fact that I is

incremented every clock cycle using the Sue unit, and Z is

initialized to the value 1 using the register number n+l.

Equation 4 determines the end of operation when I reaches

the value m. Equation 5 means that h has n inputs from

308

the n registers, one output from register number n+2

which is initialized to the value g(E), and an input I

which is the output of the SUC unit.

(51 ,u-Recursion is

represented using the circuit shown in

Figure 5.

Ready

Fig. 5. P-Recursion Implementation

The circuit is represented in RSL as follows:

Initp(O,m ; 1,argr ;

2,argz; . . . ; n,arg,)

Result = po sue (Result)

Ready - eq?(O) g(m,Result))

First equation is used to initialize

n+l

register with h

arguments and m value, second equation is used to indi-

cate that the unit sue has an input from a register initial-

ized with a value 0 and the output of

sue is the Result,

and third statement is used for comparing sue output with

m.

From the previous transformation method we see that each

construct in ASL has an equivalent representation in RSL.

The equivalence between ASL and RSL represents the base

for the automatic transformation procedure for any algo

rithm specified using ASL to RSL.

S.Implementation of an Inner-product Cell

An example of an Inner-product cell is introduced in

this section. The cell has three inputs a, 6, and c, and an

output d The function of the cell is specified by:

d- a*b + c

The implementation of this equation is

done in two levels.

At the first level we need to multiply

A

and B. The multi-

plication is done in a recursive way using repetitive addi-

tion. This can be simply described by the following high

level subroutine:

multiplication (n,m)

begin

ij( n = 0) then result = m

else

6 egin

temp = multiplication

((n-l),m)

result = addition (temp, m)

end

end

The second level of the process is an implementation of the

addition operation. The addition is done also recursively

and can be described as follows:

addition (n, m)

begin

if

( n = 0) then result = m

else

begin

temp

= addition ((n-l),m)

result = increment (temp)

end

end

The operation of the cell can be described as follows:

inner-product (a, 6,~)

begin

if

( c = 0) then

result

= multiplication ( a,b)

else

begin

temp

= inner-product (a, b, c-1)

result = increment

( temp )

end

end

Other representations may be found for the inner-product

cell. We are not trying to find all representations at this

level, but we want to mention that different representa-

tions can affects the final design.

ASL Representation

To make the example clear we describe the code at three

different levels, First is the code of the multiplication unit

which is required by the inner-product cell. Secondly, the

code for the addition unit which is required by the multi-

plication unit. Finally, the code of the inner-product cell.

Multiplication unit code:

pro(n ,O) = W.

addI. av 1, am, argd -

add(rlXw 1, am, argd,rl39( arg 1, am am))

pro(n,m+l) - addl,p,m,pro(n,m))

Addition Unit code: add(n,O) - v;(n).

Q(avl,w2,ard

= ~(rl3S(wl,w~~ar~d

add(n,m+l) = Q(n,m,add(n,m)).

Inner-product

cell code:

inner-product(a,b,O) = pro(eta?(a,b,O),q$(a,b,O))

add-one(argl,arg2,arg,,arg,) - X(rl$ argl,arg2,args,arg,))

inner-product(a,b,c+l) -

add-one(a,b,c,inner-product(a,b >c))

309

RSL Representation

The RSL specification is divided to three parts as the ASL

specification.

The multiplication unit code:

Result1 - zero 1 Rule, (1)

Result, - muzl(argl , w2, avs # 1) 1 Rules (2)

Results - muxe(argl , arg2) args # 3) 1

Rule5 (3)

Result, = add,s(Result2 , Result8

# add) 1

Rule7 (4)

Initp(O,m ;

1,n) 1

Rules-l (5)

SUC,,,~,,~ = zero ready 1 Rules+ (6)

I = pf sue(l) 1 Rules-s (‘1

Ready = eq?(I,m) 1

Rules+ (8)

Result - ~ro(n,~,~k,,,,~ # addIs) I Rules-6 (9)

Comparing the ASL and RSL specifications we see that

statement

1

in RSL is corresponding to the first statement

in ASL and is obtained using rule 4 in the transformation

procedure, statements 2-4 are corresponding to the second

statement in ASL and is obtained by applying rule 5 twice

and rule 7 once, and statements 5-8 are corresponding to

the third ASL statement and is obtained by applying rule 8

once. A schematic diagram for pro is shown in Figure 6.

I

Fig.

6

Implementation of the unit

pro.

Result

The addition unit code:

Result1 = muzI(arg, # 1) I Rule, (10)

Result:!

= muz2(argr ,

arg2, args # 3) 1

Rule6 (11)

Results =

Q(Result2#suc) 1 Rule7 (12)

IGtp(O,m ; 1,n) I

Rules+ (13)

s~ccod,ol - Result yDdy I Rules+ (14)

I = pf WC(I) 1 Rule8+ (15)

Ready =

eq?(I,m) I Rules+

(16)

Result - add(n;l,pLrtl # C?) I Rules-5 (17)

A schematic diagram for the function

add

is shown in Fig-

ure 7.

Result

Fig. 7. Implementation of the unit

add.

The inner-product cell code:

Result1 = muzI(argI, arg2,

args, arg4 #

1) I

Rules(18)

Result9 = muzz(arg,, arg2, arga, arg4

# 4) I Rule6(19)

Results = temp(Resultl,

Result2 #

pro) 1 Rule, (20)

Result4 = mudam, arg2, am, arg4 # 4) I Rub(21)

Results = add-one(Result4 # X) I Rule7

(22)

Initp(O,m ; 1,n) I

Rules1

(23)

SUC,,,~,~~ - resultgady 1 Rule- (24)

I - pf sue(1) I Rules+ (25)

Ready - eq?(Z,m) I Rules+ (26)

Result - inner-product (n , I,

P&,.lts#add-one) IRub- (27)

A schematic diagram for

pro

is shown in Figure 8

6. Conclusions

In this paper a procedure for transforming a

p-recursive algorithm to a digital architecture is intro-

duced. A new Language (ASL) which is based on p-recur-

sive functions is used for representing the algorithm. ASL

has a limited number of constructs used to represent any

algorithm. An (RSL) is used to represent the components

and connectivity of the digital architecture that executes

310

Fig. 8. Implementation of the unit inner-product.

the given algorithm. RSL representation is obtained using

a correctness preserving set of transformations. An

automated procedure is introduced that transforms an ASL

representation to its isomorphic RSL representation.

References

[AG83] P. E. Agre, “Designing a High-level Silicon Com-

piler,” Proc. IEEE Int. Conf, on Computer

Design: VLSI in Computers, Port Chester, NY,

1983.

[BA81]

(BM88]

P-321

[ Jo831

P-61

[KG=1

[KG851

M. R. Barbacci, “Instruction Set Processor

Specifications (ISPS): The Notation and its

applications,” IEEE Trans. Computers, Vol. C-

30, pp. 2440, Jan. 1981.

C.H. van Berkel, M. Rem and R. W. Saeijs,

‘VLSI Programming,” Intl Conf. on Computer

Design: VLSI in Computer and processors, pp.

152-156, Oct. 1988.

L. J. Hafer and A. C. Parker, “Automated Syn-

thesis of Digital Hardware,” IEEE Trans. Com-

puter, Vol. C-31, pp. 93-109, Feb. 1982.

S. D. Johnson, “Synthesis of Digital Designs from

Recursion Equations,” Ph.D. Dissertation, Comp.

SC. Dept., Indiana Uni., 1983.

S. C. Kleene, “General Recursive Functions of

Natural Numbers,” Mathematische Annalen, pp.

727-742,

1936.

D. Knapp, J. Granacki, and A. C. Parker, “An

expert Synthesis System,” Proc. of the Int. Conf.

on Computer Aided Design, pp. 414424, 1983.

T. J. Kowalski, D. J. Geiger, W. H. Wolf, and A.

C. Parker, “The VLSI Design automation assis-

tant: From Algorithms to Silicon,” IEEE Design

[K084]

1~~831

[LP81]

[NA81]

(PF82)

IQU841

[RA85]

[ TK89]

[TR87]

[TS84]

T. J. Kowalski, “The VLSI Design Automation

Assistant: A Knowledge-based Expert System,”

Ph.D. thesis, CMU,

1984.

T. J. Kowalski and D. E. Thomas, “The VLSI

Design Automation Assistant: Prototype Sys-

tern,” Twenty Design Automation Conf. Proc.,

Miami, pp. 479-483, 1983.

H. L. Lewis and C. H. Papadimitriou, Elements

of the Theory of Computation, Prentice-Hall,

Inc.,

1981.

A.

Nagle, ‘Heuristic Optimization of Microcon-

trollers,” Proc. 18th Design Automation Conf.,

1981.

C. Niessen, C.H. van Berkel, M. Rem, and R. W.

Saeiji, ‘VLSI Programming and Silicon Compila-

tion; A novel Approach from Philips Research,”

Intl Conf. on Computer Design: VLSI in Com-

puter and processors, pp. 150-151, Oct. 1988.

K. Palem, D. S. Fussel, and A. J. Welch, “High-

level Optimization in a Silicon Compiler,” Tech.

Rep. TR-215, Dept. of Computer Sciences,

University of Texas, Austin, TX,

1982.

P. Quinton, “Automatic Synthesis of Systolic

Arrays From Uniform Recurrent Equations,”

Proc. of the

11

th, Annual Intl Symp. on Com-

puter Architecture, pp. 208-214, 1984.

S. K. Rao, “Regular Iterative Algorithms and

Their Implementations on Processor Arrays,”

Ph.D. Dissertation, Dept. of Electrical Eng.,

Stanford Uni.,

1985.

T. Tanaka, T. Kobayashi and 0. Karatsu,

‘HARP: Fortran to Silicon,” IEEE Trans. on

computer-aided design, vol. 8., no. 6., pp. 649-

660, June 1989.

H. Trickey, “Flamel: A High Level Hardware

Compiler,” IEEE Trans. on Computer Aided

Design, vol. CAD-6, no. 2, pp. 259-269, March

1987.

C. J. Tseng, “Automated Synthesis of Data

Paths in Digital Systems,” Ph.D. Dissertation,

CMU, Apr. 1984.

and Test, pp.

33-43,

Aug.

1985.

311