A Hardware Architecture of an XML/XPath Broker for Content-Based Publish/Subscribe Systems
DOI: 10.1109/ReConFig.2010.23 Conference: ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 13-15 December 2010, Proceedings
In this paper, we present a novel hardware-based XML/XPath broker architecture for content-based Publish/ Subscribe systems. Our broker architecture includes processors to parse XML published content and XPath subscriptions, a matching engine to match subscriptions against publications, and components to forward either subscriptions or notifications based on content. While software techniques are traditionally employed, our broker architecture performs concurrent tasks and provides high performance. Moreover, the architecture can work efficiently in mobile networks by employing small-sized memory modules. Our results, obtained from a prototype FPGA, reveal that processing and matching hundreds of subscriptions can be achieved in some cases with a throughput exceeding 350 Mbps, if a 50-MHz clock is used.
Available from: Huazhong Yang
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ABSTRACT: Publish/Subscribe (Pub/Sub) is becoming an increasingly popular message delivery technique in the Internet of Things (IoT) era. However, classical Publish/Subscribe is not suitable for some emerging IoT applications such as smart grid, transportation and sensor/actuator applications due to its lack of QoS capability. To meet the requirements for QoS in IoT message delivery, in this paper we propose the first Publish/Subscribe message broker with the ability to actively schedule computation resources to guarantee QoS requirements. We abstract the message matching algorithm into a task graph to express the data flow, forming a task-based stream matching framework. Based on the framework, we explore a message dispatching algorithm called Smart Dispatch and a task scheduling algorithm called DFGS to guarantee different QoS requirements. Experiments show that, the QoS-aware system can support more than 10x throughput than QoS-ignorant systems in representative Smart Grid cases. Also, our system shows near-linear scalability on a commodity multi-core machine.
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ABSTRACT: The extensible markup language XML is a standard information representation tool and is playing an increasingly important role in many fields, like database and web services. XML parsing is a core task in XML processing, and many XML parsers are presented both in software and hardware community. In order to accelerate XML parsing, parallel XML parsing method is introduced. In this paper, we detail the design of a parallel speculative Dom-based XML parser (PSDXP) which is implemented of Field Programmable Gate Array (FPGA). Both two threads parallelism and four threads parallelism PSDXPs are implemented on a Xilinx Virtex-5 board. The former can achieve 0.5004 CPB and 1.998 Gbps, and the later capable of running at 0.2505 CPB and 3.992 Gbps.
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