Conference Paper

A Flexible Model of a CMOS Field Programmable Transistor Array Targeted for Hardware Evolution

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Abstract

This article focuses on the properties of a fine grained re- configurable transistor array currently under test at the Jet Propulsion Laboratory (JPL). This Field Programmable Transistor Array (FPTA), is integrated on a Complementary Metal-Oxide Semiconductor (CMOS) chip. The FPTA displrrys advantageous features for hardware evolutionary experiments when comparing to programmable circuits with a coarse level of granularity. Even though this programmable chip is configured at a transistor level, its architecture is flexible enough to implement standard analog and digital circuits ' building blocks with a higher level of complexity. This model and a first set of evolutionary experiments have been recently introduced; here, the objective is further illustrating its flexibility and versatility for the implementation of a variety of circuits in comparison with other models of re- configurable circuits. Some evolutionary experiments are also presented, serving as a basis for the authors to devise an improved model for the FPTA, to be manufactured in a near future.

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... Reconfigurable circuit typically consists of a grid-like layout with a certain number of different resources (transistors [4], gates, logic cells or another, e.g. RTL-level components [5]), programmable interconnection matrix and necessary volume of a configuration memory. ...
... General purpose fine-grained reconfigurable architectures for digital circuits, such as e.g. FPGAs or FPTAs [4], must obviously have almost complete interconnection network to achieve efficient-enough mapping of a circuit to the available resources. On the contrary, coarse-grained architectures may have the interconnection network more specialized (e.g. ...
... Only two of the polymorphic gates have been physically fabricated so far; remaining polymorphic gates were either simulated or tested in a FPTA [4]. For instance, the 6-transistor NAND/NOR gate controlled by V dd was fabricated in a 0.5-micron HP technology [12]. ...
Article
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This article is dealing with a development of custom chip expander platform with the possibility of accurate temperature control and integration of additional silicon-based features. Such platform may serve as a useful tool which facilitates the burdens connected with measurement and analysis tasks of experimental semiconductor structures. The devised solution provides the functionality of carrier substrate (Al2O3 compound) with CTE compatibility to the experimental silicon chip and is fully customizable with respect to a particular chip. It also allows achieving an easy fan-out of small-diameter chip terminals into a larger, more convenient area and placement of chip specimens conveniently into space-constrained chamber of the AFM microscopes, probe stations, etc. Real application of the developed chip expander platform is demonstrated in context of digital reconfigurable circuits based on polymorphic electronics. In this case the chip expander with attached polymorphic chip REPOMO is thermally stabilized at an ambient temperature level up to approximately 135˚C and its sensitivity to this phenomenon is demonstrated.
... Reconfigurable circuit typically consists of a matrix with a certain number of different elements (transistors [4], gates, logic cells or another, e.g. RTL-level components [5]), programmable interconnection matrix and necessary volume of a configuration memory. ...
... General purpose finegrained reconfigurable architectures for digital circuits, such as e.g. FPGAs or FPTAs [4], must obviously have almost complete interconnection network to achieve efficientenough mapping of a circuit to the available resources. By contrast, coarse-grained architectures may have the interconnection network more specialized (e.g. ...
... Only two of the polymorphic gates have been physically fabricated so far; remaining polymorphic gates were either simulated or tested in a FPTA [4]. For instance, the 6transistor NAND/NOR gate controlled by Vdd was fabricated in a 0.5-micron HP technology [12]. ...
Conference Paper
Full-text available
Nowadays there can be evidently identified several important application fields, such as evolvable hardware, fault-tolerant architectures or circuit development, where the exploitation of partial reconfiguration principles may bring significant benefits. For conventional digital designs, a wide range of solutions comprising fine- to coarse-grained architectures are available on the market or e.g. as virtual reconfigurable circuits. But for polymorphic digital circuits (polymorphic digital circuit is able to perform more than one function, it typically has one stable structure for all functions and an actually performed function depends on a state of an environment) only one small-scale solution has been reported so far - the REPOMO. In this paper, main attention is given to the proposal of an approach with increased flexibility, where the resulting capabilities are demonstrated.
... Analogue reconfigurable chips can be made of various basic units-Configurable Analogue Blocks (CAB), the type and granularity of the CAB in hand depending on a particular purpose of the chip. For experimental purposes, fine-grained reconfigurable architectures are often used, sometimes going even down to the transistor level as in [72] where a Field Programmable Transistor Array (FPTA) is used. Other architectures use additional devices: multiplexers-Programmable Analog Multiplexer Array (PAMA) [49] or CABs with the pulse-based communication (Palmo 1 ) [46,31]. ...
... At this stage of our investigation, a basic circuitry is identified in a form of an Operational Transconductance Amplifier, OTA, an active electronic device whose operation can be controlled by a current source. Therefore, CABs in our design are thought to be somewhere in the middle of the granularity scale, i.e. between a purely transistorbased [72] and a more complex unit which contains, for example, a whole OpAmp. Moreover, in [23] OTAs are identified as one of the building blocks for an optimal level of the CAB granularity. ...
Article
Future computing machines will have to meet increasing requirements regarding the computational power and the efficient use of resources. Whatever the technology may be, in all likelihood it will be based on parallel operation of a large number of interconnected nanoscale units. Further challenges lie in the choice of basic units and their mutual communication. Moreover, an additional design challenge comes from the sensitivity to environmental variations which is pronounced at such a low scale. Biological creations are living examples of similar designs—they are built of a number of cells, numbers ranging from one to thousands of millions. The cells are organised in a particular way and interconnected by subtle mechanisms in achieving the ultimate common goal—the preservation of viability. In doing so, living systems incessantly adapt to ever-varying environments. In this paper, we investigate adaptive mechanisms at a very low level–the protocell level–and consider a minimal living system in a form provided by chemoton theory by Tibor Ganti. We suggest that adaptive traits of the Chemoton be used as guidelines for the design of an adaptive cell within a modular man-made system. As a proof of concept, we propose a basic circuitry in silicon and argue in favour of such implementation of the proposed adaptive cell.
... Although a variety of evolution-based software environments have successfully been developed for evolutionary designs (Levine, 1994) (Heitkötter, 1997) (van Lent, 1999) (Wall, 1999) (Bennett, 1999), a tool like EHWPack was needed due to a number of factors: (a) the currently available evolutionary software packages implement general-purpose genetic algorithms running on various workstations and under different operating systems, but a dedicated genetic algorithm is needed for circuit design; (b) public domain software is available for genetic algorithm, circuit simulation, graphical interface, PC-board control and network communication, however no software integrates all these components into a single environment; (c) the genetic algorithm for circuit design using both software simulation and hardware implementation must be evaluated on a single platform; (d) the tool must be user friendly and transparent, such that experimentalists (not necessarily experts in software simulation on supercomputer) located at different sites can use it; and finally, (e) the evolutionary design of portable circuits can only be achieved by integrating results from software simulation and hardware execution in the same experimental environment ). ...
... The platform is quite flexible and supports implementation of both analog and digital circuits. While previous works [1], [2] illustrated the implementation of several conventional building blocks for electronic circuits such as logical gates, transconductance amplifiers, filters, gaussian neuron, etc., this paper illustrates the automatic design of the rather more unconventional circuits for combinatorial fuzzy logics. ...
Conference Paper
Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, comments on selected applications, and presents a perspective on the development of the field. A fine-grained Field Programmable Transistor Array (FPTA) architecture for reconfigurable hardware is presented as an example of an initial effort toward evolution-oriented devices. Evolutionary experiments in simulations and with a FPTA chip in-the-loop demonstrate automatic synthesis of electronic circuits. Unconventional circuits, for which there are no textbook design guidelines, are particularly appealing to evolvable hardware. To illustrate this situation, one demonstrates here the evolution of circuits implementing parametrical connectives for fuzzy logics. In addition to synthesizing circuits for new functions, evolvable hardware can be used to preserve existing functions and achieve fault-tolerance, determining circuit configurations that circumvent the faults. These characteristics are extremely important for enabling spacecraft to survive harsh environments and to have long life. Expanding reconfiguration to other types of spacecraft hardcore (i.e. optics, MEMS, etc.) could lead to evolvable space systems
... Stoica, 1999]. However, they too suffer from low fidelity between simplified models and actual hardware operation [Zebulum R.S., Stoica A., Keymeulen D., 2000]. A third approach is to evolve assemblies of actual macroscopic electronic components [Matthew J. Streeter, Martin A. Keane, and John R. Koza, 2003]. ...
... The platform is quite flexible and supports implementation of both analog and digital circuits. While previous works [l], [2] illustrated the implementation of several conventional building blocks for electronic circuits such as logical gates, transconductance amplifiers, filters, gaussian neuron, etc., this paper illustrates the automatic design of the rather more unconventional circuits for combinatorial fuzzy logics. ...
Conference Paper
Full-text available
Evolvable Hardware (EHW) refers to HW design and self reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing also a set of selected applications. A fine-grained Field Programmable Transistor Array (FPTA) architecture for reconfigurable hardware is presented as an example of an initial effort toward evolution-oriented devices. Evolutionary experiments in simulations and with a FPTA chip in-the-loop demonstrate automatic synthesis of electronic circuits. Unconventional circuits, for which there are no textbook design guidelines, are particularly appealing to evolvable hardware. To illustrate this situation, one demonstrates here the evolution of circuits implementing parametrical connectives for fuzzy logics. In addition to synthesizing circuits for new functions, evolvable hardware can be used to preserve existing functions and achieve fault-tolerance, determining circuit configurations that circumvent the faults. In addition, we illustrate with an example how evolution can recover functionality lost due to an increase in temperature. In the particular case of space applications, these characteristics are extremely important for enabling spacecraft to survive harsh environments and to have long life
... In one case, unconstrained evolution allows the free exploration of the search space, with no topological restrictions -this can lead to new, (patentable) designs. The second approach uses the FPTA model introduced in [7] and further detailed along with various evolutionary experiments in [8][9][10]. Different loads were used in experiments to explore their influence on the convergence of the evolutionary algorithm. ...
Article
This paper introduces the concept of polymorphic electronics,(polytronics) – referring ,to electronics ,with superimposed,built-in functionality. A function change does not require switches/reconfiguration as in ,traditional approaches. Instead, the change comes from modifications in the characteristics of devices involved in the circuit, in response to controls such as temperature, power supply voltage (VDD), control signals, light, etc. The paper illustrates polytronic circuits in which the control is done by temperature, morphing signals, and VDD respectively. Polytronic circuits are obtained byevolutionary,design /evolvable hardware ,techniques. These techniques are ideal for the polytronics design, a new area that lacks design guidelines/know-how,- yet the requirements/objectives are easy to specify and test. The circuits are evolved/synthesized in two,different modes. The first mode explores an unstructured space, in which transistors can be interconnected freely in any,arrangement,(in simulations only). The second mode,uses a Field Programmable,Transistor Array (FPTA) model, and the circuit topology is sought as a mapping onto a programmable ,architecture (these experiments are performed,both ,in simulations ,and ,on FPTA ,chips). The experiments,demonstrated the synthesis of polytronic circuits by evolution. The capacity of storing/hiding “extra” functions provides for watermark/invisible functionality, thus polytronics may,find uses in intelligence/security applications. KEY WORDS: Evolvable Hardware, polytronics,
... Different loads were used in experiments to explore their influence on the convergence of the evolutionary algorithm. The second approach uses the FPTA model introduced in [7] and further detail ed along with various evolutionary experiments in8910. This approach has the advantage that its solution can be implemented after evolution, or evolved directly in hardware on a programmable FPTA chip. ...
Conference Paper
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. The study of intrinsic hardware evolution relies heavily on commercial FPGA devices which can be configured in real time to produce physical electronic circuits. Use of these devices presents certain drawbacks to the researcher desirous of studying fundamental principles underlying hardware evolution, since he has no control over the architecture or type of basic configurable element. Furthermore, analysis of evolved circuits is difficult as only external pins of FPGAs are accessible to test equipment. After discussing current issues arising in intrinsic hardware evolution, this paper presents a new test platform designed specifically to tackle them, together with experimental results exemplifying its use. The results include the first circuits to be evolved intrinsically at the transistor level. 1 Introduction In recent years, evolutionary algorithms (EAs) have been applied to the design of electronic circuitry with significant results being attained using both computer simulations...
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