Conference Paper

Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems

Integrated Syst. Lab., ETH, Zurich
DOI: 10.1109/ISCAS.2006.1693531 Conference: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece
Source: DBLP

ABSTRACT

The paper describes an algorithm and a corresponding VLSI architecture for the implementation of linear MMSE detection in packet-based MIMO-OFDM communication systems. The advantages of the presented receiver architecture are low latency, high-throughput, and efficient resource utilization, since the hardware required for the computation of the MMSE estimators is reused for the detection. The algorithm also supports the extraction of soft information for channel decoding

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    • "The SSFE forms a class of tree search algorithms that provides a feasible implementation complexity for moderately correlated channels [3]. The LMMSE and SSFE hardware implementations are at a mature stage and different implementations can be found in [4] and [5]. A unified hardware solution for both LMMSE and SSFE is difficult to implement. "
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    • "As for the hardware implementations, systolic array is the most common architecture to support massive computing parallelism. Designs can be a 2-D tri-array [2] or a 1-D linear array [6],[7]. In [3], a complicated function unit in charge of all iterations is used. "
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    ABSTRACT: Complex-valued QR factorization is a fundamental but computationally intensive operation commonly used in various MIMO signal detection algorithms. In this paper, a novel factorization scheme based on Givens rotations and symmetrical nullification was devised. The proposed scheme successfully integrates the MMSE criterion into factorization and can achieve better BER performance. Instead of working on a complex-valued domain, the scheme starts with a block-wise symmetric real-valued matrix counterpart. By exploiting the symmetrical property, the proposed scheme effectively reduced almost half of the computing complexity. Based on the presented scheme, a novel systolic array design featuring fully parallel and deeply pipelined processing was developed subject to the EWC 802.11n recommendation. Architecture optimization measures such as look-up table (LUT) free CORDIC implementations and hardware sharing among scaling operations were employed to minimize the hardware design complexity. Post layout simulation results using TSMC 0.18μm process indicate the proposed design, with a gate count of 233K and a maximum clock rate of 120 MHz, can admit a new 4×4 complex matrix for MMSE based factorization in every 8 clock cycles (66.7ns).
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