Conference Paper

Adaptive chip-package thermal analysis for synthesis and design

DOI: 10.1145/1131720 Conference: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006
Source: DBLP


Ever-increasing integrated circuit (IC) power densities and peak temperatures threaten reliability, performance, and economical cool- ing. To address these challenges, thermal analysis must be embedded within IC synthesis. However, detailed thermal analysis requires ac- curate three-dimensional chip-package heat flow analysis. This has typically been based on numerical methods that are too computation- ally intensive for numerous repeated applications during synthesis or design. Thermal analysis techniques must be both accurate and fast for use in IC synthesis. This article presents a novel, accurate, incremental, self-adaptive, chip-package thermal analysis technique, called ISAC, for use in IC synthesis and design. It is common for IC temperature variation to strongly depend on position and time. ISAC dynamically adapts spatial and temporal modeling granularity to achieve high efficiency while maintaining accuracy. Both steady-state and dynamic thermal analysis are accelerated by the proposed heterogeneous spatial res- olution adaptation and temporally decoupled element time marching techniques. Each technique enables orders of magnitude improvement in performance while preserving accuracy when compared with other state-of-the-art adaptive steady-state and dynamic IC thermal analysis techniques. Experimental results indicate that these improvements are sufficient to make accurate dynamic and static thermal analysis prac- tical within the inner loops of IC synthesis algorithms. ISAC has been validated against reliable commercial thermal analysis tools using in- dustrial and academic synthesis test cases and chip designs. It has been implemented as a software package suitable for integration in IC synthesis and design flows and has been publicly released.

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    • "There exist different approaches in order to model the thermal behavior of microelectronic devices. Many of them are based on the equivalency of thermal and electrical energy flows [2][3][10][13]. These approaches use electrical circuits utilizing resistors and capacitors to model the spreading of heat within the material. "
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    ABSTRACT: As transistor dimensions are shrinking into regions of only a few atomic layers, designers are faced with various prob-lems including increased reliability and power issues. Since these problems are amplified by higher circuit temperatures, this paper proposes an approach for the fine-grained modeling of tempera-ture distribution in many-core systems based on Networks-on-Chip. With this model, algorithms can be developed that consider the significant impact of temperature ─ e.g. on performance, power or reliability. To simulate the dynamic nature of tempera-ture, the thermal properties of according integrated systems are modeled through the instantiation of equivalent RC-circuits. This approach exploits the dualism between electrical and thermal flows of energy. Finally, an application with system control for task mapping and power management exemplifies the proposed simulation methodology.
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    • "A thermal model can be converted to an equivalent electrical model dual [5]. Temperature estimation tools [5], [11] based on this model are often used in academic settings. In our work we have used Hotspot [5] "
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    ABSTRACT: Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and thread- level parallelism by issuing instructions from different threads in the same cycle. However, the issues of power and thermal man- agement hinder SMT processors fabricated in nano-scale tech- nologies. Power and thermal issues in SMT processors not only limit the achievable performance, but also have a direct impact on the cost and viability of these processors. While several per- formance simulation tools to explore the performance aspect of SMT processors early in their design phase exist, there is a lack of early power and performance evaluation tools for SMT pro- cessors. To this end, we have developed PTSMT: a tightly cou- pled power, performance and thermal exploration tool for SMT processors. In this paper, we demonstrate that PTSMT can au- tomatically and effectively accomplish power, performance and thermal exploration of SMT processors at various levels of de- sign hierarchy, at the application level, microarchitecture level, and physical level. Our experimental results show that: at the application level, number of contexts into which an application is divided could affect performance by 2.2x, energy by 52%, and peak temperature by 35oC; and at the microarchitecture level, context swapping during run time could reduce energy by 9% and improve performance by 8%. These observations indicate the size of the design space which can be explored using PTSMT.
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    • "This section introduces the IC thermal analysis problem and describes the system architecture of ISAC. Note that this version of ISAC has grown in capabilities and techniques compared with a more preliminary system with the same name [12]. However, we thought it would be least confusing to current users of the software to keep the same name. "
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    ABSTRACT: Chip-package thermal analysis is necessary for the design and synthesis of reliable, high-performance, low-power, compact integrated circuits (ICs). Many methods of IC thermal analysis suffer performance or accuracy problems that prevent use in IC synthesis and hinder use in architectural design. This article describes ISAC, a novel, fast, accurate thermal analysis system for use in IC synthesis and design. We present new, cooperative, temporal and spatial adaptation methods to dramatically accelerate accurate analysis. The proposed system unifies steady-state, time-domain, and frequency-domain analysis techniques. It is composed of our spatially-adaptive multigrid iterative solver, a new temporally and spatially adaptive asynchronous time marching solver, and a new spatially-adaptive frequency-domain moment matching solver. Together, these cooperative adaptation and multi-domain analysis techniques allow the proposed system to efficiently solve the static, short time scale, and long time scale variants of the IC thermal analysis problem. Experimental results demonstrate significant performance improvement over existing thermal analysis solutions. Our spatial adaptation techniques bring a 21.6times -690.0times speedup over recently-published steady-state thermal analysis techniques. Our unified spatial and temporal adaptation techniques, within our asynchronous time marching method, bring a 1,071times -1,890times speedup over other widely-used, time-domain thermal analysis techniques with less than 0.5% error. Our spatial adaptation techniques enable the efficient use of our frequency-domain thermal analysis technique, which brings a 10times - 100times speedup over the fastest-known time-domain technique, when used for long time scale thermal analysis. The thermal analysis system described in this article has been implemented as a C/C++ library that has been publicly released for free academic and personal use
    Preview · Conference Paper · Dec 2006
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