Conference Paper

Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration.

DOI: 10.1109/DATE.2011.5763244 Conference: Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011
Source: DBLP


This paper introduces the first available tool flow for Dynamic Partial Reconfiguration on the Spartan-6 family. In addition, the paper proposes a new configuration method called Fast Start-up targeting modern FPGA architectures, where the FPGA is configured in two-steps, instead of using a single (monolithic) full device configuration. In this novel approach, only the timing-critical modules are loaded at power-up using the first high-priority bitstream, while the non-timing critical modules are loaded afterwards. This two-step or prioritized FPGA start-up is used in order to meet the extremely tight startup timing specifications found in many modern applications, like PCI-express or automotive applications. Finally, the developed tool flow and methods for Fast Start-up have been used and tested to implement a CAN-based automotive ECU on a Spartan-6 evaluation board (i.e., SP605). By using this novel approach, it was possible to decrease the initial bitstream size and hence, achieve a configuration time speed-up of up to 4.5×, when compared to a standard configuration solution.

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    • "As seen from Fig. 5b, P init _1toB is generated from P init _Bto1 and F B .ncd as opposed to [7]. In [7], a custom software was used to obtain P init _1toB.bit by removing zero-frames from F B .bit. 4. For all i except 1, take the difference, F i minus F B (from F B to F i ). "
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    ABSTRACT: This paper presents a new Dynamic Partial Self Reconfiguration (DPSR) flow for Xilinx FPGAs. Leveraging the Xilinx FPGA Editor and PlanAhead tools, we provide two implementation approaches that enable partial reconfiguration for large configuration changes without Xilinx's paid tool. The flow is difference-based but still allows a modular design, which is made up of Partial Reconfiguration (PR) modules and a static design. It works regardless of the amount of difference between PR modules. We call this flow DPSR-LD, where LD stands for Large Differences. DPSR-LD is an enabler especially for Spartan-6 FPGA family., as Xilinx currently supports PR on Spartan-6 only through the difference-based flow and only for small differences. DPSR-LD also includes an ICAP controller that makes DPSR possible and offers bitstream compression.
    Full-text · Conference Paper · Dec 2013
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    ABSTRACT: In this paper we present novel techniques, methods and tool flows that enable embedded systems implemented on FPGAs to start-up under tight timing constraints (i.e., hard deadlines). Meeting the application deadline is achieved by exploiting the FPGA programmability in order to implement a two-stage system start-up approach, as well as a suitable memory hierarchy. This reduces the FPGA configuration time as well as the startup time of the embedded software. Thereby the start-up time for timing-critical parts of a design neither dependent on the complexity nor on the start-up time of the complete system. An automotive case study is used to demonstrate the feasibility and quantify the benefits of the proposed approach.
    No preview · Conference Paper · Jan 2011
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    ABSTRACT: The sequential execution of processing elements by time-multiplexing FPGA resources using single-island partial reconfiguration allows for resource-efficient designs in comparison to static FPGA implementations. Designing a processing chain for such a system requires the chain to be partitioned into reconfigurable modules, which can be sequentially executed. For this task, we will present an approach to partition an existing digital signal processing chain into separate modules with the goal to obtain a balanced logic occupation. Furthermore, we will show how the overhead of context switching can be reduced by frame-aware data processing and we will introduce a context-annotation scheme for synchronous data flow graphs. After applying our findings to a reconfigurable digital audio broadcasting receiver and quantifying the benefits and drawbacks of time-multiplexed execution, we will finally show that the time-multiplexed execution of receiver components decreases the resource consumption as compared to the static design.
    No preview · Conference Paper · Jan 2012
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