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Contactless testing: Possibility or pipe-dream?
Abstract and Figures
The traditionally wired interfaces of many electronic systems are in many applications being replaced by wireless interfaces. Testing of electronic systems (both integrated circuits and printed circuit boards) still requires physical electrical contact through probe needles and/or sockets. This paper addresses the state-of-the-art, options, and hurdles-still-to-take of contactless testing, which would resolve many test challenges due to shrinking size and pitch of pads and pins and inaccessibility of advanced assembly techniques as System-in-Package (SiP) and 3D stacked ICs.
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... Cette solution vise à réaliser une méthode de test sans contact complète pour les wafers. Le coeur de cette technique consiste en une antenne qui fonctionne en émetteur-récepteur [86], [87], [88]. ...
Les étapes de test en production sont basées à ce jour sur des contrôles optiques (AOI), inspection des joints de soudures par Rayons-X (AXI), électriques (ICT) et tests fonctionnels. Face à la multiplication et à la miniaturisation des composants, la cohabitation de plusieurs technologies (numérique, analogique, radiofréquence, puissance…) sur le même PCB (Printed Circuit Board), les moyens de test listés précédemment ne sont plus suffisants pour répondre complètement aux exigences de couverture de tests en production, car peu performants et coûteux en temps de développement et de cycle de test.L'objectif de cette thèse CIFRE avec ACTIA Automotive en collaboration avec le laboratoire LAAS-CNRS est de définir une stratégie de test en production innovante et adaptée aux produits à forte densité en envisageant dans un premier temps toutes les techniques existantes ou à développer. Pour ce faire, nous avons abordé dans cette thèse, des améliorations à apporter aux méthodologies de test existantes et proposé également des approches de test utilisables en amont de la production des PCBAs (Printed Circuit Board Assemblies) à haute densité et à signaux rapides.Premièrement, nous avons introduit une nouvelle technique sans contact pour tester des PCBAs lorsque l’accès physique de test est très limité. La technique consiste à utiliser des sondes de champ magnétique proche, qui détectent la distribution de champ magnétique émanant de certains composants montés sur le PCB dans le but de tester leur présence sur la carte et leur valeur par la suite. Deuxièmement, une approche de test utilisant des signatures thermiques infrarouges est présentée. Cette technique peut détecter les défauts d’assemblage du composant tel que sa présence, sa valeur et dans certain cas son état de santé, ce qui permet de conclure sur l’état de défaut du PCBA. Afin d’évaluer la pertinence de ces deux techniques, plusieurs scénarios de défaut ont été considérés et analysés avec un algorithme de détection de valeurs aberrantes. Sur plusieurs cas, les défauts de fabrication sont discriminés avec des marges importantes, tout en tenant compte de la variabilité de spécification des composants.Finalement, une technique pour regagner de l’accessibilité de test sur des pistes de transmission de signal de haute fréquence est présentée. La technique consiste à utiliser de petites ouvertures dans le masque de soudure directement au-dessus des pistes portant des signaux digitaux. Les conducteurs exposés sont mis en contact avec une sonde à bout déformable, conducteur et anisotrope. La faisabilité industrielle de cette technique a été testée sur un prototype que nous avions développé en collaboration avec la filiale d’ACTIA Group : ACTIA Engineering Services.
... On the other hand, if the ATE is equipped with a wireless transceiver while the same wireless transceivers are deployed within the dies test vectors from the ATE will be received directly by the wireless nodes without the need for contact probe into each die in the wafer. However, to facilitate wafer testing using wireless nodes, power also need to be delivered to the DUT from the probe card wirelessly, which can be a major challenge [25]. We advocate a hybrid approach to be used for wafer testing in which power is transferred using contact probes while wireless nodes are used for faster test delivery. ...
On-chip wireless interconnects have been proposed to provide energy-efficient data communication paths between cores in System-on-Chips (SoCs) in the multi and many-core era. Networks-on-Chips (NoCs) when interconnecting hundreds of cores consume large amounts of energy and suffer from high and unpredictable latency due to congestion at intermediate routers. Wireless interconnects alleviate this problem by providing direct single-hop links between distant cores in the chip. While various wireless NoC (WiNoC) architectures have been proposed and evaluated in the in the past decade this technology is not yet adopted in the mainstream industry. In order to benefit from the past decade of research in WiNoC designs a few important myths regarding wireless interconnects need to be dispelled while propelling the research to tangible technology transfer. In this paper several vectors that define the design space of WiNoCs will be identified while highlighting the state-of-the-art accomplishments in those directions by leading research groups. This will be followed by identifying the future direction that needs to be pursued to make WiNoCs a mainstream reality. At the end a few potential high-impact use-cases for wireless interconnects are discussed.
... Even though the characterisation of the core circuit is highly desired, it is mostly impossible to measure the output signals of these parts directly due to the imposed parasitics and loading effects of the contact pad and measurement facilities. The use of contactless measurements becomes increasingly significant for such core circuits, without the need for pads connected to the core circuit manufactured [1,[5][6][7]. However, most of the contactless measurement techniques are developed for deployment at Printed Circuit Board (PCB) level [8,9]. ...
This paper presents a bridged contactless measurement technique that can measure the resonant frequency and quality factor of a fully-integrated powered off voltage-controlled oscillator (VCO). Unlike the use of the conventional two-coil inductive link, the proposed technique uses an additional inductor to bridge the coupling between the LC tank and the external inductor serving measurement purposes. This makes it possible to examine the on-chip high frequency oscillator with an off-chip inductor at Printed Circuit Board (PCB) level. As an example, a K-band VCO as well as the proposed test structure have been designed and simulated using 0.13 μm CMOS technology. The quality factor and operating frequency of the oscillator are measured using the proposed contactless technique through extraction from the frequency response of a bridged inductive link. The efficiency of the method has been validated by full wave electromagnetic simulation. As a reference, the characterization of the oscillator is also obtained using the Cadence Spectre RF and Mentor Graphic’s Calibre PEX commercial Electronic Design Automation (EDA) software. The results of these two solutions agree considerably well, which supports the feasibility and potentials of using this technique for contactless measurements.
... Wireless testing aims to replace probe needles with contactless circuits that link the wafer and ATE. Efforts are also spent on contact-less testing [20], which by definition does not cause any probe damage. The potential technologies for wireless testing include radio-frequency (RF), near-field, and optical communication. ...
This second part addresses a selection of topics related to Electromagnetic interference (EMI) issues in three-dimensional integrated components. Details about Through Silicon Via (TSV) technology, modelling and parasitic effects are introduced in the first part, then key concepts such as signal integrity (SI), power integrity (PI), and Electromagnetic Interference are introduced.
... Antenna is very important and critical element in many RF applications, wireless communications, integrated passive devices (IPD), and power harvesting systems. High-gain antenna is required to overcome the limited output power of the silicon-based transmitter and the great free-space propagation loss at very high frequencies as the output power of transmitter antenna and the receiver antenna sensitivity are limited by the breakdown voltage and noise factor of CMOS transistors [6]- [10]. ...
This paper presents a Novel TSV-Based power harvesting system for low-power applications. The proposed system can harvest the energy from the coupling power between the signal through silicon vias (TSVs) in the 3D-SoC. The proposed system consists of three modules: energy source, energy harvesting which is based on TSV-based patch antenna, and power management module. The energy harvester module consists of three sub-modules: TSV-based patch antenna, 8-stage voltage multiplier and regulator, and energy storage. TSV technology is used to build an antenna on high resistivity substrate to be used as a transducer for the energy harvester system. The characteristic of this antenna is a function of TSV diameter, TSV length, and silicon resistivity. Compared to conventional on-chip antennas which suffers from low gain and low radiation efficiency, our novel antenna provides better performance parameters such as higher radiation pattern efficiency and higher gain as the antenna delivers a high gain of 5.8 dBi and the radiation efficiency is 86% over the prescribed range of frequencies. The proposed antenna is centered at 2.4 GHz with 200 MHz bandwidth. The overall area of the proposed antenna is 400µm×100µm. Building the antenna using TSV technology not only improves the performance, but also improves the isolation between the antenna and other active circuits. Simulations show that we are able to obtain dc voltage up to 2.5 V which is suitable for many low-power applications.
Radio frequency electromagnetic noise (RF) of anthropogenic origin has been shown to disrupt magnetic orientation behavior in some animals. Two sources of natural RF might also have the potential to disturb magnetic orientation behavior under some conditions: solar RF and atmospheric RF. In this review, we outline the frequency ranges and electric/magnetic field magnitudes of RF that have been shown to disturb magnetoreceptive behavior in laboratory studies and compare these to the ranges of solar and atmospheric RF. Frequencies shown to be disruptive in laboratory studies range from 0.1 to 10 MHz, with magnetic magnitudes as low as 1 nT reported to have effects. Based on these values, it appears unlikely that solar RF alone routinely disrupts magnetic orientation. In contrast, atmospheric RF does sometimes exceed the levels known to disrupt magnetic orientation in laboratory studies. We provide a reference for when and where atmospheric RF can be expected to reach these levels, as well as a guide for quantifying RF measurements.
As a solution to the need for efficient characterization of the vertical interconnection array, this paper presents an indirect contact probing method, adopting a dielectric contactor. The dielectric contactor protects vertical interconnections, resolves the issue of probe misalignments, and increases the coupling between probe tips and devices under test (DUTs). The characterization procedure is composed of the extraction of the dielectric contactor characteristic, the indirect contact measurement of DUTs, and de-embedding to obtain the DUT characteristics. To realize the multiport measurement, we propose an approximate method to formulate the scattering matrix of the dielectric contactor. For the design of calibration vias, the coaxial transmission line model with lumped elements is used, enhancing the available bandwidth of measurement. To verify the proposed method, a two-port network of two vias is characterized by numerical simulations up to 20 GHz. With the presented measurement setup, three cases of two vias are characterized up to 12 GHz. For the testing approach, DUTs containing open and short defects are fully tested by observing impedance curves up to 20 GHz.
A non-contact TSV fault detection method is proposed using capacitive coupled probing. The proposed method detects TSV faults by eye-pattern diagrams of extracted EM-modeled transfer characteristics. The TSV and a capacitive coupling is modeled using full wave analysis. Because the measurement is conducted by moving one top probe without contact alignment, it can achieve the fast detection. Moreover, several TSVs can be covered at one measurement. From the experimental results, the fault existence and no. of faults can be detected with good resolutions.
This chapter presents a novel design and characterization of the spiral inductor based on through silicon via (TSV) technology. An equivalent lumped model is introduced where this model is based on physics and takes into consideration TSV nonlinearities and skin effect.
A highly accurate closed-form expression for the TSV-based spiral inductor equivalent inductance is presented. This closed form is the first in literature. Moreover, this form is verified against a large number of electromagnetic (EM) simulations for different setups and shows excellent agreement with < 5 % error.
The various arguments for introducing optical interconnections to
silicon CMOS chips are summarized, and the challenges for optical,
optoelectronic, and integration technologies are discussed. Optics could
solve many physical problems of interconnects, including precise clock
distribution, system synchronization (allowing larger synchronous zones,
both on-chip and between chips), bandwidth and density of long
interconnections, and reduction of power dissipation. Optics may relieve
a broad range of design problems, such as crosstalk, voltage isolation,
wave reflection, impedence matching, and pin inductance. It may allow
continued scaling of existing architectures and enable novel highly
interconnected or high-bandwidth architectures. No physical breakthrough
is required to implement dense optical interconnects to silicon chips,
though substantial technological work remains. Cost is a significant
barrier to practical introduction, though revolutionary approaches exist
that might achieve economies of scale. An Appendix analyzes scaling of
on-chop global electrical interconnects, including line inductance and
the skin effect, both of which impose significant additional constraints
on future interconnects
A non-contact method for parallel testing of system-in-package (SiP) assemblies is presented. This technology allows for JTAG testing of partially or fully populated SiPs in wafer form, in advance of final packaging. The technology utilizes non-contact GHz short-range, near field communications to transfer bi-directional data to SiP substrates; creating a wireless test access port or WTAP. The system is integrated with a standard probe card to deliver power and wireless signals. The wireless probes convert high frequency RF (GHz) transceiver signals to standard tester ATE logic levels and allow the use of standard probers and JTAG testers. In addition, all transceivers (DUTand probe) use antenna structures and electronics that are fully CMOS compliant. Enhancing the economics of SiP manufacture by enabling parallel non-contact testing of SiPs before packaging is a key benefit of this technology.
A method for wireless, noncontact testing of semiconductor wafers is presented. The technology applies to chips with active electronics, including standard integrated circuits (ICs), which require testing at the wafer level. The technology relies on short-range, near field communications to transfer data at gigabit per second rates between the probe card and the device under test (DUT) on a wafer. The probe consists of a CMOS device with micro antenna structures and transceiver circuits. Each antenna and transceiver circuit is capable of probing one input/output (I/O) site on the DUT. Each I/O site on the DUT is connected to a single antennae and transceiver circuit, which is designed into the DUT. The antennae and transceiver circuits can be incorporated into the DUT without any impact on performance or real estate. The main advantage of noncontact wafer probing is higher reliability (less retest, no pad scrub marks), added functionality (higher test frequencies at higher pin densities), and increased throughput (higher parallelism, reduced alignment tolerance, less maintenance, and less downtime). The wireless probes interface to standard automated test equipment (ATE) while all antenna structures and electronics needed on the DUT are fully CMOS compliant
The basic technologies which have been developed to satisfy the production of semiconductor devices are outlined. These technologies commenced with point-contact alloy and alloy-diffused techniques. Diffusion was then developed giving the means of making structures such as rectifiers, transistors and thyristors. Silicon planar technology and the assembly methods used are then described as applied to discrete devices and integrated circuits (both bipolar and m.o.s.). © 1973, The Institution of Electronic and Radio Engineers. All rights reserved.
Two RF techniques are combined with capacitive coupling interconnect to form ultra-wide-bandwidth impulse interconnect and RF interconnect in 3D IC technology. They achieve 10Gb/s/pin and 11Gb/s/pin transmission with 2.7mW/pin and 4.35mW/pin power consumption, respectively, using the MIT Lincoln Lab 3D 0.18mum CMOS, an 8times improvement over previous work
A transceiver for inductive-coupling is realized. By using a pulse-shaping circuit, the transmitter energy is 0.11pj/b. Due to device scaling from 180nm CMOS to 90nm CMOS, the receiver energy is 0.03pJ/b. The overall energy dissipation is 20times lower than previous work, without degrading the data rate of 1Gb/s.
IBM's current semiconductor manufacturing processes are summarized. Briefly outlined are highlights of salient features of semiconductor manufacturing that established IBM leadership and direction for embarking on VLSI production. Some of these features are taken from papers already published; others are from articles in this issue of the IBM Journal of Research and Development ranging from silicon crystal growth through quality control and automated logistics and dispositioning of tested product.
An inductive-coupling link is presented whose data rate is 11Gb/s for a distance of 15mum and 8.5Gb/s for a distance of 45mum. The data rate is increased by 11 to 8.5x over past inductive-coupling links. Compared with the capacitive-coupling link (Cu et al., 2007), the communication distance is extended by 5x for the same data rate, layout area, and bit error rate (BER), even by using a less- scaled device technology, 0.18mum CMOS.